| Component-based design approach for multicore SoCs W Cesario, A Baghdadi, L Gauthier, D Lyonnard, G Nicolescu, Y Paviot, ... Proceedings of the 39th annual Design Automation Conference, 789-794, 2002 | 247 | 2002 |
| Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip D Lyonnard, S Yoo, A Baghdadi, AA Jerraya Proceedings of the 38th annual Design Automation Conference, 518-523, 2001 | 224 | 2001 |
| Butterfly and Benes-based on-chip communication networks for multiprocessor turbo decoding H Moussa, O Muller, A Baghdadi, M Jézéquel 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 82 | 2007 |
| Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder H Moussa, A Baghdadi, M Jézéquel Proceedings of the 45th Annual Design Automation Conference, 429-434, 2008 | 79 | 2008 |
| A generic wrapper architecture for multi-processor SoC cosimulation and design S Yoo, G Nicolescu, D Lyonnard, A Baghdadi, AA Jerraya Proceedings of the ninth international symposium on Hardware/software …, 2001 | 78 | 2001 |
| ASIP-based multiprocessor SoC design for simple and double binary turbo decoding O Muller, A Baghdadi, M Jézéquel Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 69 | 2006 |
| An efficient architecture model for systematic design of application-specific multiprocessor SoC A Baghdadi, D Lyonnard, NE Zergainoh, AA Jerraya Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 68 | 2001 |
| Low-complexity pipelined architecture for FBMC/OQAM transmitter J Nadal, CA Nour, A Baghdadi IEEE Transactions on Circuits and Systems II: Express Briefs 63 (1), 19-23, 2015 | 67 | 2015 |
| From parallelism levels to a multi-ASIP architecture for turbo decoding O Muller, A Baghdadi, M Jézéquel IEEE transactions on very large scale integration (VLSI) systems 17 (1), 92-102, 2008 | 66 | 2008 |
| An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory SI Han, A Baghdadi, M Bonaciu, SI Chae, AA Jerraya Proceedings of the 41st annual Design Automation Conference, 250-255, 2004 | 64 | 2004 |
| Exploring parallel processing levels for convolutional turbo decoding O Muller, A Baghdadi, M Jezequel 2006 2nd International Conference on Information & Communication …, 2006 | 62 | 2006 |
| Design and evaluation of a novel short prototype filter for FBMC/OQAM modulation J Nadal, CA Nour, A Baghdadi IEEE access 6, 19610-19625, 2018 | 60 | 2018 |
| Hardware prototyping of FBMC/OQAM baseband for 5G mobile communication systems J Nadal, CA Nour, A Baghdadi, H Lin RSP 2014: IEEE International Symposium on Rapid System Prototyping, 135-141, 2014 | 52 | 2014 |
| Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems A Baghdadi, NE Zergainoh, WO Cesario, AA Jerraya IEEE Transactions on Software Engineering 28 (9), 822-831, 2002 | 52 | 2002 |
| A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding P Murugappa, R Al-Khayat, A Baghdadi, M Jezequel 2011 Design, Automation & Test in Europe, 1-6, 2011 | 46 | 2011 |
| Energy-efficient fpga implementation for binomial option pricing using opencl VM Morales, PH Horrein, A Baghdadi, E Hochapfel, S Vaton 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 44 | 2014 |
| Design space exploration for hardware/software codesign of multiprocessor systems A Baghdadi, N Zergainoh, W Cesario, T Roudier, AA Jerraya Proceedings 11th International Workshop on Rapid System Prototyping. RSP …, 2000 | 43 | 2000 |
| FPGA-based radar signal processing for automotive driver assistance system J Saad, A Baghdadi, F Bodereau 2009 IEEE/IFIP International Symposium on Rapid System Prototyping, 196-199, 2009 | 33 | 2009 |
| Parallel and flexible 5G LDPC decoder architecture targeting FPGA J Nadal, A Baghdadi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (6 …, 2021 | 32 | 2021 |
| Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder H Moussa, A Baghdadi, M Jézéquel 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 97-100, 2008 | 31 | 2008 |
