Purushotham M V
Purushotham M V
Nokia Bell labs
Adresse e-mail validée de nokia-bell-labs.com
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A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding
P Murugappa, R Al-Khayat, A Baghdadi, M Jezequel
2011 Design, Automation & Test in Europe, 1-6, 2011
352011
Parameterized area-efficient multi-standard turbo decoder
P Murugappa, A Baghdadi, M Jézéquel
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 109-114, 2013
132013
Area and throughput optimized ASIP for multi-standard turbo decoding
R Al-Khayat, P Murugappa, A Baghdadi, M Jézéquel
2011 22nd IEEE International Symposium on Rapid System Prototyping, 79-84, 2011
92011
FPGA prototyping and performance evaluation of multi-standard turbo/LDPC encoding and decoding
P Murugappa, JN Bazin, A Baghdadi, M Jézéquel
2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP …, 2012
62012
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes
P Murugappa, V Lapotre, A Baghdadi, M Jezequel
2013 International symposium on rapid system prototyping (RSP), 87-93, 2013
52013
Stopping-free dynamic configuration of a multi-ASIP turbo decoder
V Lapotre, P Murugappa, G Gogniat, A Baghdadi, M Hübner, JP Diguet
2013 Euromicro Conference on Digital System Design, 155-162, 2013
52013
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context
V Lapotre, P Murugappa, G Gogniat, A Baghdadi, JP Diguet, JN Bazin, ...
2013 IEEE computer society annual symposium on VLSI (ISVLSI), 40-45, 2013
42013
A dynamically reconfigurable multi-ASIP architecture for multistandard and multimode turbo decoding
V Lapotre, P Murugappa, G Gogniat, A Baghdadi, M Hübner, JP Diguet
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (1), 383-387, 2015
32015
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder
V Lapotre, P Murugappa, G Gogniat, A Baghdadi, JP Diguet, JN Bazin, ...
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 493-496, 2013
32013
ASIP design for multi-standard channel decoders
P Murugappa, A Baghdadi, M Jezequel
Advanced Hardware Design for Error Correcting Codes, 151-175, 2015
22015
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture
V Lapotre, M Hübner, G Gogniat, P Murugappa, A Baghdadi, JP Diguet
2013 8th International Workshop on Reconfigurable and Communication-Centric …, 2013
2013
Flexible Multi-ASIP SoC for Turbo/LDPC Decoder
P Murugappa, P Reddy, R Alkhayat, JN Bazin, A Baghdadi, F Clermidy, ...
Technical Session 1: FPGA Technologies
Q Tang, M Tuna, H Mehrez, D Uliana, K Kepa, P Athanas, K Nasartschuk, ...
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