| Two-dimensional simulation of local oxidation of silicon: calibrated viscoelastic flow analysis V Senez, D Collard, P Ferreira, B Baccus IEEE Transactions on Electron Devices 43 (5), 720-731, 1996 | 80 | 1996 |
| Device and method for alignment of vertically stacked wafers and die JH Zhang, W Kleemeier, P Ferreira, RK Sampson US Patent 8,569,899, 2013 | 30 | 2013 |
| Mechanical stress analysis of an LDD MOSFET structure P Ferreira, V Senez, B Baccus IEEE Transactions on Electron Devices 43 (9), 1525-1532, 1996 | 20 | 1996 |
| Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC) T Devoivre, M Lunenborg, C Julien, JP Carrere, P Ferreira, WJ Toren, ... Proceedings of the 2002 IEEE International Workshop on Memory Technology …, 2002 | 19 | 2002 |
| Method for production process for the local interconnection level using a dielectric conducting pair on pair P Coronel, F Leverd, P Ferreira US Patent 6,689,655, 2004 | 18 | 2004 |
| Elimination of stress induced silicon defects in very high density SRAM structures P Ferreira, RA Bianchi, F Guyader, R Pantel, E Granger 31st European solid-state device research conference, 427-430, 2001 | 17 | 2001 |
| Simulation of advanced field isolation using calibrated viscoelastic stress analysis V Senez, D Collard, P Ferreira, B Baccus Proceedings of 1994 IEEE International Electron Devices Meeting, 881-884, 1994 | 9 | 1994 |
| Finite element optimization of a MOSFET structure: the roll of interlayer material for residual stress reduction P Ferreira, V Senez, B Baccus, J Varon, J Lebailly Proceedings of International Electron Devices Meeting, 503-506, 1995 | 6 | 1995 |
| Device and method for alignment of vertically stacked wafers and die JH Zhang, W Kleemeier, P Ferreira, RK Sampson US Patent 9,324,660, 2016 | 5 | 2016 |
| Method for forming contact openings on a MOS integrated circuit P Ferreira, P Coronel US Patent 6,911,366, 2005 | 5 | 2005 |
| Study of local silicon oxidation with calibrated nitride model P Ferreira, V Senez, D Collard, B Baccus ESSDERC'94: 24th European Solid State Device Research Conference, 259-262, 1994 | 4 | 1994 |
| Device and method for alignment of vertically stacked wafers and die JH Zhang, W Kleemeier, P Ferreira, RK Sampson US Patent 10,615,125, 2020 | 3 | 2020 |
| Precise real time and position low pressure control of chemical mechanical polish (cmp) head JH Zhang, P Ferreira, C Goldberg US Patent App. 12/946,155, 2012 | 2 | 2012 |
| Cu CMP Edge Uniformity Improvement Studies for 32 nm Technology Node and Beyond JH Zhang, L Economikos, W Tseng, J Choi, Q Fang, TJ Tang, J Salfelder, ... MRS Online Proceedings Library (OPL) 1249, 1249-E01-06, 2010 | 2 | 2010 |
| Study of the 300-mm CoSi2 defects induced by Soft Sputter Etch process before cobalt deposition—characterization, design of experiment and 200/300 mm comparison A Humbert, C Regnier, G Braeckelmann, MT Basso, P Ferreira Materials Science and Engineering: B 114, 209-213, 2004 | 2 | 2004 |
| Introduction du calcul mécanique généralisé dans la simulation bidimensionnelle de procédés technologiques silicium P Ferreira Lille 1, 1999 | 2 | 1999 |
| Method for protecting the gate of a transistor and corresponding integrated circuit P Ferreira US Patent 8,823,107, 2014 | 1 | 2014 |
| Optimizing Stressor Film Deposition Sequence in Polish Rate Order for Best Planarization JH Zhang, C Xiao, JW Strane, R Venigalla, L Economikos, L Hall, J Chen, ... MRS Online Proceedings Library 1335, 15-20, 2011 | 1 | 2011 |
| Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process P Ferreira, P Coronel US Patent 6,797,597, 2004 | 1 | 2004 |
| Device and method for alignment of vertically stacked wafers and die JH Zhang, W Kleemeier, P Ferreira, RK Sampson US Patent 11,205,621, 2021 | | 2021 |
