Hamid R. Zarandi
Hamid R. Zarandi
Associate Professor, Department of Computer Engineering, Amirkabir University of Technology
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Dependability analysis using a fault injection tool based on synthesizability of HDL models
HR Zarandi, SG Miremadi, A Ejlali
Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003
Matrix codes: Multiple bit upsets tolerant method for SRAM memories
C Argyrides, HR Zarandi, DK Pradhan
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007
A fast and accurate fault tree analysis based on stochastic logic implemented on field-programmable gate arrays
H Aliee, HR Zarandi
IEEE Transactions on Reliability 62 (1), 13-22, 2012
A hybrid fault injection approach based on simulation and emulation co-operation
A Ejlali, SG Miremadi, H Zarandi, G Asadi, SB Sarmadi
2003 International Conference on Dependable Systems and Networks, 2003 …, 2003
DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors
MH Mottaghi, HR Zarandi
Microprocessors and Microsystems 38 (1), 88-97, 2014
Fault injection into verilog models for dependability evaluation of digital systems
HR Zarandi, SG Miremadi, A Ejlali
Parallel and Distributed Computing, International Symposium on, 281-281, 2003
SEU-mitigation placement and routing algorithms and their impact in SRAM-based FPGAs
HR Zarandi, SG Miremadi, DK Pradhan, J Mathew
8th International Symposium on Quality Electronic Design (ISQED'07), 380-385, 2007
Fault injection into SRAM-based FPGAs for the analysis of SEU effects
G Asadi, SG Miremadi, HR Zarandi, A Ejlali
Proceedings. 2003 IEEE International Conference on Field-Programmable …, 2003
Aligner: A process-in-memory architecture for short read alignment in rerams
F Zokaee, HR Zarandi, L Jiang
IEEE Computer Architecture Letters 17 (2), 237-240, 2018
A fault-tolerant low-energy multi-application mapping onto NoC-based multiprocessors
F Khalili, HR Zarandi
2012 IEEE 15th International Conference on Computational Science and …, 2012
HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors
M Kishani, HR Zarandi, H Pedram, A Tajary, M Raji, B Ghavami
Design Automation for Embedded Systems 15, 289-310, 2011
Fast SEU detection and correction in LUT configuration bits of SRAM-based FPGAs
HR Zarandi, SG Miremadi, C Argyrides, DK Pradhan
2007 IEEE International Parallel and Distributed Processing Symposium, 1-6, 2007
A fault‐tolerant core mapping technique in networks‐on‐chip
F Khalili, HR Zarandi
IET Computers & Digital Techniques 7 (6), 238-245, 2013
Two efficient software techniques to detect and correct control-flow errors
HR Zarandi, M Maghsoudloo, N Khoshavi
2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing …, 2010
Fault tree analysis using stochastic logic: A reliable and high speed computing
H Aliee, HR Zarandi
2011 Proceedings-Annual Reliability and Maintainability Symposium, 1-6, 2011
Multiple upsets tolerance in SRAM memory
C Argyrides, HR Zarandi, DK Pradhan
2007 IEEE International Symposium on Circuits and Systems, 365-368, 2007
Designing fault-tolerant network-on-chip router architecture
A Eghbal, PM Yaghini, H Pedram, HR Zarandi
International Journal of Electronics 97 (10), 1181-1192, 2010
Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs
G Asadi, SG Miremadi, HR Zarandi, A Ejlali
10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004 …, 2004
Investigation of transient fault effects in synchronous and asynchronous network on chip router
PM Yaghini, A Eghbal, H Pedram, HR Zarandi
Journal of Systems Architecture 57 (1), 61-68, 2011
Analysis of transient faults on a mips-based dual-core processor
I Faraji, M Didehban, HR Zarandi
2010 International Conference on Availability, Reliability and Security, 125-130, 2010
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