| Performance analysis of low-power 1-bit CMOS full adder cells AM Shams, TK Darwish, MA Bayoumi IEEE transactions on very large scale integration (VLSI) systems 10 (1), 20-29, 2002 | 705 | 2002 |
| A novel high-performance CMOS 1-bit full-adder cell AM Shams, MA Bayoumi IEEE Transactions on circuits and systems II: Analog and digital signal …, 2000 | 300 | 2000 |
| NEDA: A low-power high-performance DCT architecture AM Shams, A Chidanandan, W Pan, MA Bayoumi IEEE transactions on signal processing 54 (3), 955-964, 2006 | 123 | 2006 |
| A structured approach for designing low power adders AM Shams, MA Bayoumi Conference Record of the Thirty-First Asilomar Conference on Signals …, 1997 | 83 | 1997 |
| Performance evaluation of 1-bit CMOS adder cells A Shams, M Bayoumi 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 27-30, 1999 | 71 | 1999 |
| A low power high performance distributed DCT architecture A Shams, W Pan, A Chidanandan, MA Bayoumi Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms …, 2002 | 50 | 2002 |
| A new full adder cell for low-power applications AM Shams, MA Bayoumi Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No. 98TB100222 …, 1998 | 47 | 1998 |
| A comparative analysis for low power motion estimation VLSI architectures MA Elgamel, AM Shams, MA Bayoumi 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and …, 2000 | 41 | 2000 |
| NEDA: A new distributed arithmetic architecture and its application to one dimensional discrete cosine transform W Pan, A Shams, MA Bayoumi 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and …, 1999 | 36 | 1999 |
| A novel low-power building block CMOS cell for adders AM Shams, MA Bayoumi 1998 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 153-156, 1998 | 24 | 1998 |
| A framework for fair performance evaluation of 1-bit full adder cells AM Shams, MA Bayoumi 42nd Midwest Symposium on Circuits and Systems (Cat. No. 99CH36356) 1, 6-9, 1999 | 22 | 1999 |
| A 108 Gbps, 1.5 GHz 1D-DCT Architecture A Shams, M Bayoumi Proceedings IEEE International Conference on Application-Specific Systems …, 2000 | 11 | 2000 |
| An enhanced low-power pipelined multiplier-accumulator for DSP applications WM Badawy, AM Shams, MA Bayoumi The 7Th NASA Symposium on VLSI, 1-2, 1998 | 10 | 1998 |
| Enhanced low power motion estimation VLSI architectures for video compression MA Elgamel, AM Shams, X Xueling, MA Bayoumi ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001 | 7 | 2001 |
| A high-performance 1D-DCT architecture A Shams, W Pan, A Chandanandan, M Bayoumi 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 5, 521-524, 2000 | 6 | 2000 |
| An enhanced low-power computational kernel for a pipelined multiplier-accumulator unit AM Shams, WM Badawy, MA Bayoumi Proceedings of the Tenth International Conference on Microelectronics (Cat …, 1998 | 4 | 1998 |
| Hybrid mesh-based/block-based motion compensation architecture AM Shams, MA Elgamel, MA Bayoumi Proceedings Second International Workshop on Digital and Computational Video …, 2001 | 3 | 2001 |
| Low Power Full Search Block Matching Motion Estimation VLSI Architectures MA Elgamel, MA Bayoumi, AM Shams, B Zavidovique Journal of Circuits, Systems, and Computers 13 (06), 1271-1288, 2004 | 2 | 2004 |
| A CNN implementation of a hysteresis chaos generator C Aissi, A Shams 1999 IEEE International Symposium on Circuits and Systems (ISCAS) 5, 631-634, 1999 | 2 | 1999 |
| High-speed and low-power architectures for a hybrid video coder AM Shams University of Louisiana at Lafayette, 2000 | | 2000 |
