| Neural network accelerator tile architecture with three-dimensional stacking AG Nowatzyk, O Temam, R Narayanaswami, UK Dasari US Patent 9,928,460, 2018 | 28 | 2018 |
| Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies UK Dasari, O Temam, R Narayanaswami, DH Woo US Patent 10,936,942, 2021 | 20 | 2021 |
| Experiences building edge TPU with chisel D Lockhart, S Twigg, R Narayanaswami, J Coriell, U Dasari, R Ho, ... 2018 Chisel Community Conference (CCC), 2018 | 10 | 2018 |
| Hardware circuit for accelerating neural network computations R Narayanaswami, DH Woo, S Gupta, UK Dasari US Patent App. 16/973,087, 2021 | 1 | 2021 |
| Neural network accelerator tile architecture with three-dimensional stacking AG Nowatzyk, O Temam, R Narayanaswami, UK Dasari US Patent 11,948,060, 2024 | | 2024 |
| Memory Sharing S Gupta, R Narayanaswami, UK Dasari, A Iranli, P Thirunagari, VV Kumar, ... US Patent App. 17/425,918, 2022 | | 2022 |
| Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies UK Dasari, O Temam, R Narayanaswami, DH Woo US Patent App. 17/186,598, 2021 | | 2021 |
| Neural network accelerator tile architecture with three-dimensional stacking AG Nowatzyk, O Temam, R Narayanaswami, UK Dasari US Patent App. 15/927,367, 2018 | | 2018 |
