| Cross-layer co-optimization of network design and chiplet placement in 2.5-D systems A Coskun, F Eris, A Joshi, AB Kahng, Y Ma, A Narayan, V Srinivas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 44 | 2020 |
| POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems Y Thonnart, S Bernabé, J Charbonnier, C Bernard, D Coriat, C Fuguet, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020 | 40 | 2020 |
| PROWAVES: Proactive runtime wavelength selection for energy-efficient photonic NoCs A Narayan, Y Thonnart, P Vivet, AK Coskun IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 30 | 2020 |
| MOCA: Memory Object Classification and Allocation in Heterogeneous Memory Systems A Narayan, T Zhang, S Aga, S Narayanasamy, A Coskun 2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2018 | 28 | 2018 |
| WAVES: Wavelength selection for power-efficient 2.5 D-integrated photonic NoCs A Narayan, Y Thonnart, P Vivet, CF Tortolero, AK Coskun 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 516-521, 2019 | 25 | 2019 |
| Development of the ABCStar front-end chip for the ATLAS silicon strip upgrade W Lu, F Anghinolfi, L Cheng, J De Witt, J Kaplon, P Keener, A Narayan, ... Journal of Instrumentation 12 (04), C04017, 2017 | 20 | 2017 |
| Architecting optically controlled phase change memory A Narayan, Y Thonnart, P Vivet, A Coskun, A Joshi ACM Transactions on Architecture and Code Optimization 19 (4), 1-26, 2022 | 16 | 2022 |
| System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications A Narayan, Y Thonnart, P Vivet, A Joshi, AK Coskun Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020 | 16 | 2020 |
| Bandwidth Allocation in Silicon-Photonic Networks Using Application Instrumentation A Narayan, A Joshi, AK Coskun IEEE High Performance Extreme Computing Conference (HPEC), 2020 | 3 | 2020 |
| System-Level Management of Silicon-Photonic Networks in 2.5 D Systems A Narayan, A Joshi, AK Coskun Silicon Photonics for High-Performance Computing and Beyond, 71-88, 2021 | 1 | 2021 |
| Energy-efficient architectures for chip-scale networks and memory systems using silicon-photonics technology A Narayan Boston University, 2021 | | 2021 |
| Temperature and Process Variation-Aware Wavelength Selection in Photonic NoCs A Narayan, Y Thonnart, P Vivet, CF Tortolero, AK Coskun Boston Area Architecture Workshop, 2019 | | 2019 |
| An Automated Framework for Memory Allocation in Heterogeneous Memory Systems A Narayan, T Zhang, S Aga, S Narayanasamy, AK Coskun Boston Area Architecture Workshop, 2018 | | 2018 |
| FPGA Acceleration of DNA Sequence Mapping A NARAYAN, A ANAND, GS PERUMAL, S JAGETIA, A SHIVALKAR | | |
| Detecting Anomalies in User Profiles in the Cloud via Machine Learning C Wong, T Tiwari, A Narayan, AK Coskun | | |
Ayse K CoskunProfessor in ECE Department, Boston UniversityVerified email at bu.edu
