Henry Duwe
Cited by
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Low-power, low-storage-overhead chipkill correct via multi-line error correction
X Jian, H Duwe, J Sartori, V Sridharan, R Kumar
Proceedings of the International Conference on High Performance Computing …, 2013
Modular design of high-throughput, low-latency sorting units
A Farmahini-Farahani, HJ Duwe III, MJ Schulte, K Compton
IEEE Transactions on Computers 62 (7), 1389-1402, 2012
Approximate bitcoin mining
M Vilim, H Duwe, R Kumar
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
Correction prediction: Reducing error correction latency for on-chip memories
H Duwe, X Jian, R Kumar
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
Rescuing uncorrectable fault patterns in on-chip memories through error pattern transformation
H Duwe, X Jian, D Petrisko, R Kumar
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture …, 2016
High performance, energy efficient chipkill correct memory with multidimensional parity
X Jian, J Sartori, H Duwe, R Kumar
IEEE Computer Architecture Letters 12 (2), 39-42, 2012
Porting CMP benchmarks to GPUs
MD Sinclair, H Duwe, K Sankaralingam
University of Wisconsin-Madison Department of Computer Sciences, 2011
Determining application-specific peak power and energy requirements for ultra-low-power processors
H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori
ACM Transactions on Computer Systems (TOCS) 35 (3), 1-33, 2017
Bespoke processors for applications with ultra-low area and power constraints
H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori
Proceedings of the 44th Annual International Symposium on Computer …, 2017
A unified framework for error correction in on-chip memories
F Sala, H Duwe, L Dolecek, R Kumar
2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016
Better-than-worst-case design: Progress and opportunities
J Cong, H Duwe, R Kumar, S Li
Journal of computer science and technology 29 (4), 656-663, 2014
Markov chain algorithms: A template for building future robust low power systems
B Deka, AA Birklykke, H Duwe, VK Mansinghka, R Kumar
2013 Asilomar Conference on Signals, Systems and Computers, 118-125, 2013
Software-based gate-level information flow security for IoT systems
H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
Exploiting application level error resilience via deferred execution
H Duwe
Enabling Effective Module-oblivious Power Gating for Embedded Processors
H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks
S Saha, H Duwe, J Zambreno
Journal of Signal Processing Systems, 1-23, 2020
Revisiting Time Remanence Clocks for Energy Harvesting Wireless Sensor Nodes
V Deep, A Mishra, D Qiao, H Duwe
Proceedings of the 7th International Workshop on Energy Harvesting & Energy …, 2019
An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators
S Saha, H Duwe, J Zambreno
2019 IEEE 30th International Conference on Application-specific Systems …, 2019
Gate-level information flow security
H Cherupalli, R Kumar, J Sartori, H Duwe
US Patent App. 16/149,748, 2019
Bespoke Processors for Applications with Ultra-Low Area and Power Constraints
H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori
IEEE Micro 38 (3), 32-39, 2018
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