| The Arm triple core lock-step (TCLS) processor X Iturbe, B Venu, E Ozer, JL Poupat, G Gimenez, HU Zurek ACM Transactions on Computer Systems (TOCS) 36 (3), 1-30, 2019 | 44 | 2019 |
| Static timing analysis of asynchronous bundled-data circuits G Gimenez, A Cherkaoui, G Cogniard, L Fesquet 2018 24th IEEE International Symposium on Asynchronous Circuits and Systems …, 2018 | 33 | 2018 |
| From signal transition graphs to timing closure: Application to bundled-data circuits G Gimenez, J Simatic, L Fesquet 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems …, 2019 | 14 | 2019 |
| Self-timed ring based true random number generator: Threat model and countermeasures G Gimenez, A Cherkaoui, R Frisch, L Fesquet 2017 IEEE 2nd International Verification and Security Workshop (IVSW), 31-38, 2017 | 9 | 2017 |
| A Self-Timed Ring based PUF G Gimenez, A Cherkaoui, L Fesquet 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems …, 2020 | 4 | 2020 |
| Circuit and method for protecting asynchronous circuits L Fesquet, A Cherkaoui, G Gimenez, R Frisch | 1 | 2020 |
| Method for generating a unique data specific to an integrated silicon circuit G Gimenez, A Cherkaoui, L Fesquet | | 2021 |
| Concevoir des circuits sécurisés à très faible consommation: une alternative basée sur l’asynchrone G Gimenez Université Grenoble Alpes, 2021 | | 2021 |
