Leonardo Ecco
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A mixed critical memory controller using bank privatization and fixed priority scheduling
L Ecco, S Tobuschat, S Saidi, R Ernst
2014 IEEE 20th International Conference on Embedded and Real-Time Computing …, 2014
Improved dram timing bounds for real-time dram controllers with read/write bundling
L Ecco, R Ernst
2015 IEEE Real-Time Systems Symposium, 53-64, 2015
Dynamic admission control for real-time networks-on-chips
A Kostrzewa, S Saidi, L Ecco, R Ernst
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 719-724, 2016
Minimizing DRAM rank switching overhead for improved timing bounds and performance
L Ecco, A Kostrzewa, R Ernst
2016 28th Euromicro Conference on Real-Time Systems (ECRTS), 3-13, 2016
Sparc16: A new compression approach for the sparc architecture
LL Ecco, BC Lopes, EC Xavier, R Pannain, P Centoducatte, ...
2009 21st International Symposium on Computer Architecture and High …, 2009
Workload-aware shaping of shared resource accesses in mixed-criticality systems
S Tobuschat, M Neukirchner, L Ecco, R Ernst
2014 International Conference on Hardware/Software Codesign and System …, 2014
Tackling the bus turnaround overhead in real-time SDRAM controllers
L Ecco, R Ernst
IEEE Transactions on Computers 66 (11), 1961-1974, 2017
Design and evaluation of compact ISA extensions
BC Lopes, L Ecco, EC Xavier, RJ Azevedo
Microprocessors and Microsystems 40, 1-15, 2016
Flexible TDM-based resource management in on-chip networks
A Kostrzewa, S Saidi, L Ecco, R Ernst
Proceedings of the 23rd International Conference on Real Time and Networks …, 2015
Adaptive load distribution in mixed-critical networks-on-chip
A Kostrzewa, S Tobuschat, L Ecco, R Ernst
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 732-737, 2017
Ensuring safety and efficiency in networks-on-chip
A Kostrzewa, S Saidi, L Ecco, R Ernst
Integration 58, 571-582, 2017
Technical report: Designing high-performance real-time SDRAM controllers for many-core systems (revision 1.0)
L Ecco, R Ernst
Technische Universitaet Braunschweig, Braunschweig, Germany, 084-201704061036, 2017
Architecting high-speed command schedulers for open-row real-time SDRAM controllers
L Ecco, R Ernst
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models
MJ Klaiber, S Vogel, A Acosta, R Korn, L Ecco, K Back, A Guntoro, ...
Proceedings of the INTelligent Embedded Systems Architectures and …, 2019
Architecture and Performance Analysis of a Multi-generation SDRAM Controller for Mixed Criticality Systems
L Ecco
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