| Onsite matrix elements of the tight-binding Hamiltonian of a strained crystal: Application to silicon, germanium, and their alloys YM Niquet, D Rideau, C Tavernier, H Jaouen, X Blase Physical Review B 79 (24), 245201, 2009 | 224 | 2009 |
| Strained Si, Ge, and Si 1− x Ge x alloys modeled with a first-principles-optimized full-zone k∙ p method D Rideau, M Feraille, L Ciampolini, M Minondo, C Tavernier, H Jaouen, ... Physical Review B 74 (19), 195208, 2006 | 193 | 2006 |
| 14nm FDSOI technology for high speed and energy efficient applications O Weber, E Josse, F Andrieu, A Cros, E Richard, P Perreau, E Baylac, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 113 | 2014 |
| Quantum calculations of the carrier mobility: Methodology, Matthiessen's rule, and comparison with semi-classical approaches YM Niquet, VH Nguyen, F Triozon, I Duchemin, O Nier, D Rideau Journal of Applied Physics 115 (5), 2014 | 70 | 2014 |
| Microscopic scale characterization and modeling of transistor degradation under HC stress YM Randriamihaja, V Huard, X Federspiel, A Zaka, P Palestri, D Rideau, ... Microelectronics Reliability 52 (11), 2513-2520, 2012 | 53 | 2012 |
| Fully atomistic simulations of phonon-limited mobility of electrons and holes in〈 001〉-,〈 110〉-, and〈 111〉-oriented Si nanowires YM Niquet, C Delerue, D Rideau, B Videau IEEE Trans. Electron Devices 59 (5), 1480-1487, 2012 | 42 | 2012 |
| Quantum modeling of the carrier mobility in FDSOI devices VH Nguyen, YM Niquet, F Triozon, I Duchemin, O Nier, D Rideau IEEE Transactions on Electron Devices 61 (9), 3096-3102, 2014 | 40 | 2014 |
| On the validity of the effective mass approximation and the Luttinger kp model in fully depleted SOI MOSFETs D Rideau, M Feraille, M Michaillat, YM Niquet, C Tavernier, H Jaouen Solid-State Electronics 53 (4), 452-461, 2009 | 35 | 2009 |
| Coupled mechanical and 3-D Monte Carlo simulation of silicon nanowire MOSFETs A Ghetti, GP Carnevale, D Rideau IEEE transactions on nanotechnology 6 (6), 659-666, 2007 | 28 | 2007 |
| Contact resistances in trigate and FinFET devices in a non-equilibrium Green's functions approach L Bourdet, J Li, J Pelloux-Prayer, F Triozon, M Cassé, S Barraud, ... Journal of Applied Physics 119 (8), 2016 | 27 | 2016 |
| Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs F Andrieu, M Cassé, E Baylac, P Perreau, O Nier, D Rideau, R Berthelon, ... 2014 44th European Solid State Device Research Conference (ESSDERC), 106-109, 2014 | 26 | 2014 |
| Characterization and modeling of gate-induced-drain-leakage F Gilibert, D Rideau, A Dray, F Agut, M Minondo, A Juge, P Masson, ... IEICE transactions on electronics 88 (5), 829-837, 2005 | 26 | 2005 |
| Analysis of defect capture cross sections using non-radiative multiphonon-assisted trapping model D Garetto, YM Randriamihaja, A Zaka, D Rideau, A Schmid, H Jaouen, ... Solid-state electronics 71, 74-79, 2012 | 23 | 2012 |
| On the accuracy of current TCAD hot carrier injection models in nanoscale devices A Zaka, Q Rafhay, M Iellina, P Palestri, R Clerc, D Rideau, D Garetto, ... Solid-state electronics 54 (12), 1669-1674, 2010 | 23 | 2010 |
| Hot carrier degradation: From defect creation modeling to their impact on NMOS parameters YM Randriamihaja, A Zaka, V Huard, M Rafik, D Rideau, D Roy, A Bravaix, ... 2012 IEEE International Reliability Physics Symposium (IRPS), XT. 15.1-XT. 15.4, 2012 | 22 | 2012 |
| Integration of SPAD in 28nm FDSOI CMOS technology TC De Albuquerque, F Calmon, R Clerc, P Pittet, Y Benhammou, ... 2018 48th European Solid-State Device Research Conference (ESSDERC), 82-85, 2018 | 21 | 2018 |
| Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET] D Rideau, A Dray, F Gilibert, F Agut, L Giguerre, G Gouget, M Minondo, ... Proceedings of the 2004 International Conference on Microelectronic Test …, 2004 | 21 | 2004 |
| The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies F Monsieur, Y Denis, D Rideau, V Quenette, G Gouget, C Tavernier, ... 2014 44th European Solid State Device Research Conference (ESSDERC), 254-257, 2014 | 18 | 2014 |
| Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility O Nier, D Rideau, YM Niquet, F Monsieur, VH Nguyen, F Triozon, A Cros, ... Journal of Computational Electronics 12, 675-684, 2013 | 16 | 2013 |
| Understanding Ge impact on VT and VFB in Si1− xGex/Si pMOSFETs A Soussou, C Leroux, D Rideau, A Toffoli, G Romano, O Saxod, G Bidal, ... Microelectronic engineering 109, 282-285, 2013 | 15 | 2013 |
