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Vassilis Paliouras
Vassilis Paliouras
Professor, Department of Electrical and Computer Engineering, University of Patras
Verified email at ece.upatras.gr - Homepage
Title
Cited by
Cited by
Year
Considering the alternatives in low-power design
T Stouraitis, V Paliouras
IEEE Circuits and Devices Magazine 17 (4), 22-29, 2001
1202001
Simplified hardware implementation of the softmax activation function
I Kouretas, V Paliouras
2019 8th international conference on modern circuits and systems …, 2019
952019
Low-power properties of the logarithmic number system
V Paliouras, T Stouraitis
Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, 229-236, 2001
952001
Low-power logarithmic number system addition/subtraction and their impact on digital filters
I Kouretas, C Basetas, V Paliouras
IEEE Transactions on Computers 62 (11), 2196-2209, 2012
562012
Multifunction architectures for RNS processors
V Paliouras, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1999
421999
A reconfigurable LDPC decoder optimized for 802.11 n/ac applications
I Tsatsaragkos, V Paliouras
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 182-195, 2017
412017
A VLSI design methodology for RNS full adder-based inner product architectures
DJ Soudris, V Paliouras, T Stouraitis, CE Goutis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1997
391997
A low-complexity combinatorial RNS multiplier
V Paliouras, K Karagianni, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
382001
A floating-point processor for fast and accurate sine/cosine evaluation
V Paliouras, K Karagianni, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000
362000
Hardware implementation of a softmax-like function for deep learning
I Kouretas, V Paliouras
Technologies 8 (3), 46, 2020
342020
A novel algorithm for accurate logarithmic number system subtraction
V Paliouras, T Stouraitis
1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996
341996
Logarithmic number system for low-power arithmetic
V Paliouras, T Stouraitis
Integrated Circuit Design: Power and Timing Modeling, Optimization and …, 2000
332000
Novel high-radix residue number system architectures
V Paliouras, T Stouraitis
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2000
312000
LDPC encoding and decoding techniques
I Tsatsaragkos, A Mahdi, N Kanistras, V Paliouras
US Patent 8,739,001, 2014
292014
A low complexity-high throughput QC-LDPC encoder
A Mahdi, V Paliouras
IEEE transactions on signal processing 62 (10), 2696-2708, 2014
292014
Approximate algorithms for identifying minima on min-sum LDPC decoders and their hardware implementation
I Tsatsaragkos, V Paliouras
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (8), 766-770, 2015
282015
Novel high-radix residue number system multipliers and adders
V Paliouras, T Stouraitis
1999 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 451-454, 1999
281999
A low-power termination criterion for iterative LDPC code decoders
G Glikiotis, V Paliouras
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005 …, 2005
252005
A low-complexity high-radix RNS multiplier
I Kouretas, V Paliouras
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (11), 2449-2462, 2009
242009
A multirate fully parallel LDPC encoder for the IEEE 802.11 n/ac/ax QC-LDPC codes based on reduced complexity XOR trees
A Mahdi, N Kanistras, V Paliouras
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (1), 51-64, 2020
232020
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