| Person identification technique using human iris recognition C Tisse, L Martin, L Torres, M Robert Proc. Vision Interface 294, 294-299, 2002 | 655 | 2002 |
| Hardware mechanisms for memory authentication: A survey of existing techniques and engines R Elbaz, D Champagne, C Gebotys, RB Lee, N Potlapally, L Torres Transactions on Computational Science IV, 1-22, 2009 | 85 | 2009 |
| Tec-tree: A low-cost, parallelizable tree for efficient defense against memory replay attacks R Elbaz, D Champagne, RB Lee, L Torres, G Sassatelli, P Guillemin International Workshop on Cryptographic Hardware and Embedded Systems, 289-302, 2007 | 74 | 2007 |
| A parallelized way to provide data encryption and integrity checking on a processor-memory bus R Elbaz, L Torres, G Sassatelli, P Guillemin, M Bardouillet, A Martinez Proceedings of the 43rd annual Design Automation Conference, 506-509, 2006 | 63 | 2006 |
| Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem C Jalier, D Lattard, AA Jerraya, G Sassatelli, P Benoit, L Torres 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 58 | 2010 |
| An adaptive message passing mpsoc framework G Marchesan Almeida, G Sassatelli, P Benoit, N Saint-Jean, S Varyani, ... International Journal of Reconfigurable Computing 2009, 2009 | 55 | 2009 |
| Hardware engines for bus encryption: a survey of existing techniques R Elbaz, L Torres, G Sassatelli, P Guillemin, C Anguille, C Buatois, ... Design, Automation and Test in Europe, 40-45, 2005 | 52 | 2005 |
| Temperature-aware distributed run-time optimization on MP-SoC using game theory D Puschini, F Clermidy, P Benoit, G Sassatelli, L Torres 2008 IEEE Computer Society Annual Symposium on VLSI, 375-380, 2008 | 51 | 2008 |
| A non-volatile run-time FPGA using thermally assisted switching MRAMS Y Guillemenet, L Torres, G Sassatelli, N Bruchon, I Hassoune 2008 International Conference on Field Programmable Logic and Applications …, 2008 | 46 | 2008 |
| Attacking randomized exponentiations using unsupervised learning G Perin, L Imbert, L Torres, P Maurine International Workshop on Constructive Side-Channel Analysis and Secure …, 2014 | 45 | 2014 |
| New nonvolatile FPGA concept using magnetic tunneling junction N Bruchon, L Torres, G Sassatelli, G Cambon IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006 | 44 | 2006 |
| Highly scalable dynamically reconfigurable systolic ring-architecture for DSP applications G Sassatelli, L Torres, P Benoit, T Gil, C Diou, G Cambon, J Galy Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 44 | 2002 |
| The secretblaze: A configurable and cost-effective open-source soft-core processor L Barthe, LV Cargnini, P Benoit, L Torres 2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011 | 43 | 2011 |
| Near-field mapping system to scan in time domain the magnetic emissions of integrated circuits T Ordas, M Lisart, E Sicard, P Maurine, L Torres International Workshop on Power and Timing Modeling, Optimization and …, 2008 | 43 | 2008 |
| Security trends for FPGAS: From secured to secure reconfigurable systems B Badrignans, JL Danger, V Fischer, G Gogniat, L Torres Springer Science & Business Media, 2011 | 39 | 2011 |
| Hs-scale: a hardware-software scalable mp-soc architecture for embedded systems N Saint-Jean, G Sassatelli, P Benoit, L Torres, M Robert IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 21-28, 2007 | 39 | 2007 |
| Volatile compounds in processed duck fillet S Lesimple, L Torres, S Mitjavila, Y Fernandez, L Durand Journal of food science 60 (3), 615-618, 1995 | 39 | 1995 |
| Evaluating the impact of task migration in multi-processor systems-on-chip GM Almeida, S Varyani, R Busseuil, G Sassatelli, P Benoit, L Torres, ... Proceedings of the 23rd symposium on Integrated circuits and system design …, 2010 | 38 | 2010 |
| Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories Y Guillemenet, L Torres, G Sassatelli IET Computers & Digital Techniques 4 (3), 211-226, 2010 | 37 | 2010 |
| Metrics for reconfigurable architectures characterization: Remanence and scalability P Benoit, G Sassatelli, L Torres, D Demigny, M Robert, G Cambon Proceedings International Parallel and Distributed Processing Symposium, 8 pp., 2003 | 34 | 2003 |
P. MAURINEUniv. Monpellier / LIRMMAdresse e-mail validée de lirmm.fr
