Anupam Chattopadhyay
Anupam Chattopadhyay
Associate Professor, SCSE, SPMS, NTU, Singapore
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Adversarial attacks and defences: A survey
A Chakraborty, M Alam, V Dey, A Chattopadhyay, D Mukhopadhyay
arXiv preprint arXiv:1810.00069, 2018
Wireless communication and security issues for cyber–physical systems and the Internet-of-Things
A Burg, A Chattopadhyay, KY Lam
Proceedings of the IEEE 106 (1), 38-60, 2017
LISA: A uniform ADL for embedded processor modeling, implementation, and software toolsuite generation
A Chattopadhyay, H Meyr, R Leupers
Processor description languages, 95-132, 2008
A blockchain framework for insurance processes
M Raikwar, S Mazumdar, S Ruj, SS Gupta, A Chattopadhyay, KY Lam
2018 9th IFIP International Conference on New Technologies, Mobility and …, 2018
The programmable logic-in-memory (PLiM) computer
PE Gaillardon, L Amarú, A Siemon, E Linn, R Waser, A Chattopadhyay, ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 427-432, 2016
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits
R Wille, O Keszocze, M Walter, P Rohrs, A Chattopadhyay, R Drechsler
2016 21st Asia and South Pacific design automation conference (ASP-DAC), 292-297, 2016
Designing and modeling MPSoC processors and communication architectures
H Meyr, O Schliebusch, A Wieferink, D Kammler, EM Witte, O Lüthje, ...
Building ASIPS: The Mescal Methodology, 229-280, 2005
Generic Side-channel attacks on CCA-secure lattice-based PKE and KEMs.
P Ravi, SS Roy, A Chattopadhyay, S Bhasin
IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020 (3), 307-335, 2020
High-performance hardware implementation for RC4 stream cipher
SS Gupta, A Chattopadhyay, K Sinha, S Maitra, BP Sinha
IEEE Transactions on Computers 62 (4), 730-743, 2012
ReVAMP: ReRAM based VLIW architecture for in-memory computing
D Bhattacharjee, R Devadoss, A Chattopadhyay
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Autonomous vehicle: Security by design
A Chattopadhyay, KY Lam, Y Tavva
IEEE Transactions on Intelligent Transportation Systems 22 (11), 7015-7029, 2020
Processor modeling and design tools
P Mishra, N Dutt
EDA for IC System Design, Verification, and Testing, 8-1-8-21, 2018
Ingredients of adaptability: a survey of reconfigurable processors
A Chattopadhyay
VLSI Design 2013, 10-10, 2013
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment
J Constantin, L Wang, G Karakonstantis, A Chattopadhyay, A Burg
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 381-386, 2015
Mind the portability: A warriors guide through realistic profiled side-channel analysis
S Bhasin, A Chattopadhyay, A Heuser, D Jap, S Picek, R Ranjan
NDSS 2020-Network and Distributed System Security Symposium, 1-14, 2020
Multistate memristive tantalum oxide devices for ternary arithmetic
W Kim, A Chattopadhyay, A Siemon, E Linn, R Waser, V Rana
Scientific reports 6 (1), 1-9, 2016
Security vulnerabilities of unmanned aerial vehicles and countermeasures: An experimental study
V Dey, V Pudi, A Chattopadhyay, Y Elovici
2018 31st international conference on VLSI design and 2018 17th …, 2018
Toward threat of implementation attacks on substation security: Case study on fault detection and isolation
A Chattopadhyay, A Ukil, D Jap, S Bhasin
IEEE Transactions on Industrial Informatics 14 (6), 2442-2451, 2017
Depth-optimal quantum circuit placement for arbitrary topologies
D Bhattacharjee, A Chattopadhyay
arXiv preprint arXiv:1703.08540, 2017
MUQUT: Multi-constraint quantum circuit mapping on NISQ computers
D Bhattacharjee, AA Saki, M Alam, A Chattopadhyay, S Ghosh
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2019
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