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Philippe Vialletelle
Philippe Vialletelle
Senior Principal Engineer, STMicroelectronics
Adresse e-mail validée de st.com
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Flexibility measures for qualification management in wafer fabs
C Johnzén, S Dauzère-Pérès, P Vialletelle
Production Planning and Control 22 (1), 81-90, 2011
612011
A literature review on sampling techniques in semiconductor manufacturing
J Nduhura-Munga, G Rodriguez-Verjan, S Dauzère-Pérès, C Yugma, ...
IEEE Transactions on Semiconductor Manufacturing 26 (2), 188-195, 2013
572013
A smart sampling algorithm to minimize risk dynamically
S Dauzere-Péres, JL Rouveyrol, C Yugma, P Vialletelle
2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 307-310, 2010
512010
A literature review on variability in semiconductor manufacturing: The next forward leap to Industry 4.0
K Dequeant, P Vialletelle, P Lemaire, ML Espinouse
2016 Winter Simulation Conference (WSC), 2598-2609, 2016
292016
Quality and exposure control in semiconductor manufacturing. Part I: Modelling
B Bettayeb, S Bassetto, P Vialletelle, M Tollenaere
International Journal of Production Research 50 (23), 6835-6851, 2012
262012
Dynamic management of controls in semiconductor manufacturing
JN Munga, S Dauzère-Pérès, P Vialletelle, C Yugma
2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 1-6, 2011
262011
Optimisation of the process control in a semiconductor company: model and case study of defectivity sampling
M Shanoun, S Bassetto, S Bastoini, P Vialletelle
International Journal of Production Research 49 (13), 3873-3890, 2011
222011
A sampling-based approach for managing lot release in time constraint tunnels in semiconductor manufacturing
A Lima, V Borodin, S Dauzère-Pérès, P Vialletelle
International Journal of Production Research 59 (3), 860-884, 2021
182021
Impact of qualification management on scheduling in semiconductor manufacturing
C Johnzén, P Vialletelle, S Dauzere-Péres, C Yugma, A Derreumaux
2008 Winter Simulation Conference, 2059-2066, 2008
162008
Finite capacity planning algorithm for semiconductor industry considering lots priority
E Mhiri, M Jacomino, F Mangione, P Vialletelle, G Lepelletier
IFAC-PapersOnLine 48 (3), 1598-1603, 2015
152015
Importance of qualification management for wafer fabs
C Johnzen, S Dauzere-Peres, P Vialletelle, C Yugma
2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 166-169, 2007
142007
A mathematical programming approach for optimizing control plans in semiconductor manufacturing
JN Munga, S Dauzère-Pérès, C Yugma, P Vialletelle
International Journal of Production Economics 160, 213-219, 2015
13*2015
Sampling-based release control of multiple lots in time constraint tunnels
A Lima, V Borodin, S Dauzère-Pérès, P Vialletelle
Computers in Industry 110, 3-11, 2019
122019
Generic data model for semiconductor manufacturing supply chains
G Laipple, S Dauzère-Pérès, T Ponsignon, P Vialletelle
2018 Winter Simulation Conference (WSC), 3615-3626, 2018
122018
A step toward capacity planning at finite capacity in semiconductor manufacturing
E Mhiri, M Jacomino, F Mangione, P Vialletelle, G Lepelletier
Proceedings of the Winter Simulation Conference 2014, 2239-2250, 2014
122014
Optimized design of control plans based on risk exposure and resources capabilities
B Bettayeb, P Vialletelle, S Bassetto, M Tollenaere
2010 International Symposium on Semiconductor Manufacturing (ISSM), 1-4, 2010
122010
Optimized management of excursions in semiconductor manufacturing
JN Munga, P Vialletelle, S Dauzere-Péres, C Yugma
Proceedings of the 2011 Winter Simulation Conference (WSC), 2100-2107, 2011
112011
Quality and exposure control in semiconductor manufacturing. Part II: Evaluation
B Bettayeb, S Bassetto, P Vialletelle, M Tollenaere
International Journal of Production Research 50 (23), 6852-6869, 2012
102012
A smart sampling scheduling and skipping simulator and its evaluation on real data sets
C Yugma, S Dauzère-Pérès, JL Rouveyrol, P Vialletelle, J Pinaton, ...
Proceedings of the 2011 Winter Simulation Conference (WSC), 1903-1912, 2011
102011
Optimizing return on inspection trough defectivity smart sampling
M Sahnoun, P Vialletelle, S Bassetto, S Bastoini, M Tollenaere
2010 International Symposium on Semiconductor manufacturing (ISSM), 1-4, 2010
102010
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