Benoît Dupont de Dinechin
Benoît Dupont de Dinechin
CTO Kalray
Verified email at - Homepage
TitleCited byYear
A clustered manycore processor architecture for embedded and accelerated applications
BD de Dinechin, R Ayrignac, PE Beaucamps, P Couvert, B Ganne, ...
2013 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2013
Time-critical computing on a single-chip massively parallel processor
BD De Dinechin, D Van Amstel, M Poulhiès, G Lager
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
A distributed run-time environment for the kalray mppa®-256 integrated manycore processor
BD de Dinechin, PG de Massas, G Lager, C Léger, B Orgogozo, J Reybert, ...
Procedia Computer Science 18, 1654-1663, 2013
Revisiting out-of-SSA translation for correctness, code quality and efficiency
B Boissinot, A Darte, F Rastello, BD De Dinechin, C Guillon
Proceedings of the 7th annual IEEE/ACM International Symposium on Code …, 2009
Guaranteed services of the NoC of a manycore processor
BD de Dinechin, Y Durand, D Van Amstel, A Ghiti
Proceedings of the 2014 International Workshop on Network on Chip …, 2014
Extended cyclostatic dataflow program compilation and execution for an integrated manycore processor
P Aubry, PE Beaucamps, F Blanc, B Bodin, S Carpov, L Cudennec, ...
Procedia Computer Science 18, 1624-1633, 2013
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources
G Giannopoulou, N Stoimenov, P Huang, L Thiele, BD de Dinechin
Real-Time Systems 52 (4), 399-449, 2016
The shift to multicores in real-time and safety-critical systems
S Saidi, R Ernst, S Uhrig, H Theiling, BD de Dinechin
Proceedings of the 10th International Conference on Hardware/Software …, 2015
Periodic schedules for cyclo-static dataflow
B Bodin, A Munier-Kordon, BD de Dinechin
The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 105-114, 2013
Code generator optimizations for the ST120 DSP-MCU core
BD de Dinechin, F de Ferriere, C Guillon, A Stoutchinin
International Conference on Compilers, Architecture and Synthesis for …, 2000
From machine scheduling to VLIW instruction scheduling
BD de Dinechin
ST Journal of Research 1 (2), 1-35, 2004
K-periodic schedules for evaluating the maximum throughput of a synchronous dataflow graph
B Bodin, A Munier-Kordon, BD de Dinechin
2012 International Conference on Embedded Computer Systems (SAMOS), 152-159, 2012
Simplex scheduling: More than lifetime-sensitive instruction scheduling
BD de Dinechin
Proceedings of the International Conference on Parallel Architecture and …, 1994
Parametric computation of margins and of minimum cumulative register lifetime dates
BD de Dinechin
International Workshop on Languages and Compilers for Parallel Computing …, 1996
A mixed-precision fused multiply and add
N Brunie, F De Dinechin, B De Dinechin
2011 Conference Record of the Forty Fifth Asilomar Conference on Signals …, 2011
Time-indexed formulations and a large neighborhood search for the resource-constrained modulo scheduling problem
BD De Dinechin
3rd Multidisciplinary International Scheduling conference: Theory and …, 2007
Network-on-chip service guarantees on the kalray mppa-256 bostan processor
BD de Dinechin, A Graillat
Proceedings of the 2nd International Workshop on Advanced Interconnect …, 2017
A ultra fast Euclidean division algorithm for prime memory systems
BD De Dinechin
Supercomputing'91: Proceedings of the 1991 ACM/IEEE Conference on …, 1991
SCAN: A heuristic for near-optimal software pipelining
F Blachot, BD de Dinechin, G Huard
European Conference on Parallel Processing, 289-298, 2006
Radiation experiments on a 28 nm single-chip many-core processor and SEU error-rate prediction
V Vargas, P Ramos, V Ray, C Jalier, R Stevens, BD De Dinechin, ...
IEEE Transactions on Nuclear Science 64 (1), 483-490, 2016
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