Alexandru Amaricai
Alexandru Amaricai
Assistant Professor of Computer Engineering, University Politehnica of Timisoara
Verified email at cs.upt.ro
Title
Cited by
Cited by
Year
Design issues and implementations for floating-point divide–add fused
A Amaricai, M Vladutiu, O Boncalo
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (4), 295-299, 2010
502010
An FPGA sliding window-based architecture Harris corner detector
A Amaricai, CE Gavriliu, O Boncalo
2014 24th International Conference on Field Programmable Logic and …, 2014
382014
FPGA design of high throughput LDPC decoder based on imprecise offset min-sum decoding
T Nguyen-Ly, K Le, F Ghaffari, A Amaricai, O Boncalo, V Savin, ...
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
362015
Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing
O Boncalo, A Amaricai, A Hera, V Savin
2014 24th International Conference on Field Programmable Logic and …, 2014
162014
Linear compositional delay model for the timing analysis of sub-powered combinational circuits
J Chen, C Spagnol, S Grandhi, E Popovici, S Cotofana, A Amaricai
2014 IEEE Computer Society Annual Symposium on VLSI, 380-385, 2014
162014
Probabilistic gate level fault modeling for near and sub-threshold CMOS circuits
A Amaricai, S Nimara, O Boncalo, J Chen, E Popovici
2014 17th Euromicro Conference on Digital System Design, 473-479, 2014
132014
FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization
S Nimara, O Boncalo, A Amaricai, M Popa
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
122016
Memory efficient FPGA implementation for flooded LDPC decoder
A Amaricai, O Boncalo, I Mot
2015 23rd telecommunications forum Telfor (TELFOR), 500-503, 2015
112015
Design of addition and multiplication units for high performance interval arithmetic processor
A Amaricai, M Vladutiu, L Prodan, M Udrescu, O Boncalo
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-4, 2007
102007
Using simulated fault injection for fault tolerance assessment of quantum circuits
O Boncalo, M Udrescu, L Prodan, M Vladutiu, A Amaricai
40th Annual Simulation Symposium (ANSS'07), 213-220, 2007
102007
Layered LDPC decoders with efficient memory access scheduling and mapping and built-in support for pipeline hazards mitigation
O Boncalo, G Kolumban-Antal, A Amaricai, V Savin, D Declercq
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (4), 1643-1656, 2018
92018
Memory trade-offs in layered self-corrected min-sum LDPC decoders
O Boncalo, A Amaricai, PF Mihancea, V Savin
Analog Integrated Circuits and Signal Processing 87 (2), 169-180, 2016
92016
Cost effective FPGA probabilistic fault emulation
O Boncalo, A Amaricai, C Spagnol, E Popovici
2014 NORCHIP, 1-4, 2014
92014
Low-precision DSP-based floating-point multiply-add fused for Field Programmable Gate Arrays
A Amaricai, O Boncalo, CE Gavriliu
IET Computers & Digital Techniques 8 (4), 187-197, 2014
92014
Ultra high throughput unrolled layered architecture for qc-ldpc decoders
O Boncalo, A Amaricai
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 225-230, 2017
82017
Design of floating point units for interval arithmetic
A Amaricai, M Vladutiu, O Boncalo
2009 Ph. D. Research in Microelectronics and Electronics, 12-15, 2009
82009
Implementation of very high radix division in FPGAs
A Amaricai, O Boncalo
Electronics letters 48 (18), 1107-1109, 2012
72012
Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment
O Boncalo, M Udrescu, L Prodan, M Vladutiu, A Amaricai
10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007
72007
Design Trade-offs in Configurable FPGA Architectures for K-Means Clustering
A Amaricai
Studies in Informatics and Control 26 (1), 43-48, 2017
62017
Configurable fpga architecture for hardware-software merge sorting
PC Petrut, A Amaricai, O Boncalo
2016 MIXDES-23rd International Conference Mixed Design of Integrated …, 2016
62016
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