Saurabh Sharma
Saurabh Sharma
Adresse e-mail validée de intel.com
Titre
Citée par
Citée par
Année
Low granularity coarse depth test efficiency enhancement
V Ranganathan, S Mandal, KA Szerszen, S Sharma, VV Chivukula, ...
US Patent 10,102,609, 2018
65*2018
Weld: A multithreading technique towards latency-tolerant VLIW processors
E Özer, TM Conte, S Sharma
International Conference on High-Performance Computing, 192-203, 2001
362001
Position-only shading pipeline
S Sharma, S Maiyuran, TA Piazza, KK Bhiravabhatla, PL Doyle, ...
US Patent 9,824,412, 2017
222017
Spectral prefetcher: An effective mechanism for L2 cache prefetching
S Sharma, JG Beu, TM Conte
ACM Transactions on Architecture and Code Optimization (TACO) 2 (4), 423-450, 2005
142005
Method and apparatus for pixel hashing
S Maiyuran, S Sharma, EJ Hoekstra, J Fernandez
US Patent App. 14/498,445, 2016
82016
Fast mechanism for accessing 2n±1 interleaved memory system
S Sharma, A Koker, A Navale
US Patent 9,268,691, 2016
62016
Frequent data value compression for graphics processing units
S Sharma, A Venkatesh, TT Schluessler, P Surti, A Koker, ...
US Patent 10,262,388, 2019
3*2019
Optimizing clipping operations in position only shading tile deferred renderers
KK Bhiravabhatla, SM Maiyuran, S Sharma
US Patent 9,846,962, 2017
32017
Hierarchical depth buffer back annotaton
V Ranganathan, S Mandal, S Sharma, VV Chivukula, KA Szerszen, ...
US Patent 10,424,107, 2019
22019
Specialized code paths in GPU processing
S Sharma, A Ventakesh, TT Schluessler, TF Raoux, RP Sathe, ...
US Patent App. 10/140,678, 2018
2*2018
Method and apparatus for adaptive pixel hashing for graphics processors
KK Bhiravabhatla, S Maiyuran, JFG Pabon, S Sharma
US Patent 9,836,809, 2017
22017
Single input multiple data processing mechanism
S Maiyuran, JFG Pabon, V Vemulapalli, CS Gurram, A Navale, S Sharma
US Patent 10,417,730, 2019
12019
System and method for performing partial cache line writes without fill-reads or byte enables
H Hashemi, S Sharma, A Koker
US Patent App. 10/146,691, 2018
2018
Method and apparatus for adaptive pixel hashing for graphics processors
KK Bhiravabhatla, S Maiyuran, JFG Pabon, S Sharma
US Patent App. 15/830,860, 2018
2018
System and method for performing partial cache line writes without fill-reads or byte enables
H Hashemi, S Sharma, A Koker
US Patent App. 15/374,630, 2018
2018
Spectral prediction: A signals approach to computer architecture prefetching
S Sharma
North Carolina State University, 2006
2006
DYNAMIC ADVANCE LOAD REMOVAL
C Rosier, S Sharma
2005
Le système ne peut pas réaliser cette opération maintenant. Veuillez réessayer plus tard.
Articles 1–17