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Dong Jiao
Dong Jiao
Verified email at umn.edu
Title
Cited by
Cited by
Year
Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network
P Zhou, D Jiao, CH Kim, SS Sapatnekar
2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011
382011
Circuit design and modeling techniques for enhancing the clock-data compensation effect under resonant supply noise
D Jiao, J Gu, CH Kim
IEEE Journal of Solid-State Circuits 45 (10), 2130-2141, 2010
232010
Deep trench capacitor based step-up and step-down DC/DC converters in 32nm SOI with opportunistic current borrowing and fast DVFS capabilities
A Paul, D Jiao, S Sapatnekar, CH Kim
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 49-52, 2013
172013
Impact of interconnect length on BTI and HCI induced frequency degradation
X Wang, P Jain, D Jiao, CH Kim
2012 IEEE International Reliability Physics Symposium (IRPS), 2F. 5.1-2F. 5.6, 2012
172012
A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise
D Jiao, CH Kim
2011 IEEE International Solid-State Circuits Conference, 272-274, 2011
162011
Design, modeling, and test of a programmable adaptive phase-shifting PLL for enhancing clock data compensation
D Jiao, B Kim, CH Kim
IEEE journal of solid-state circuits 47 (10), 2505-2516, 2012
152012
The dependence of BTI and HCI-induced frequency degradation on interconnect length and its circuit level implications
X Wang, Q Tang, P Jain, D Jiao, CH Kim
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (2), 280-291, 2014
142014
Measurement, analysis and improvement of supply noise in 3D ICs
P Jain, D Jiao, X Wang, CH Kim
2011 Symposium on VLSI Circuits-Digest of Technical Papers, 46-47, 2011
122011
Enhancing beneficial jitter using phase-shifted clock distribution
D Jiao, J Gu, P Jain, C Kim
Proceedings of the 2008 international symposium on Low Power Electronics …, 2008
102008
Integrated Circuit Active Power Supply Regulation
D Jiao, H Li, R Wang, HF Huang, Y Chen
US Patent App. 12/501,375, 2010
42010
Circuit techniques for enhancing the clock data compensation effect under resonant supply noise
D Jiao, J Gu, CH Kim
2009 IEEE Custom Integrated Circuits Conference, 29-32, 2009
42009
Circuit modeling and design techniques for efficient power delivery under resonant supply noise
D Jiao
University of Minnesota, 2011
2011
Ci it T hi f E h i th Circuit Techniques for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise
D Jiao, J Gu, CH Kim
Impact of Interconnect Length on BTI and HCI Induced Frequency BTI and HCI Induced Frequency Degradation
X Wang, P Jain, D Jiao, CH Kim
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