| Clock-skew optimization for peak current reduction P Vuillod, L Benini, A Bogliolo, G De Micheli Proceedings of 1996 International Symposium on Low Power Electronics and …, 1996 | 109 | 1996 |
| Clock skew optimization for peak current reduction L Benini, P Vuillod, A Bogliolo, G De Micheli High Performance Clock Distribution Networks, 5-18, 1997 | 38 | 1997 |
| Improvements to Boolean resynthesis L Amarú, M Soeken, P Vuillod, J Luo, A Mishchenko, J Olson, R Brayton, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 755-760, 2018 | 22 | 2018 |
| Enabling exact delay synthesis L Amarú, M Soeken, P Vuillod, J Luo, A Mishchenko, PE Gaillardon, ... 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 352-359, 2017 | 22 | 2017 |
| Synthesis of low-power selectively-clocked systems from high-level specification L Benini, P Vuillod, G De Micheli, C Coelho Proceedings of 9th International Symposium on Systems Synthesis, 57-63, 1996 | 21 | 1996 |
| Logic optimization and synthesis: Trends and directions in industry L Amarú, P Vuillod, J Luo, J Olson Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 19 | 2017 |
| Iterative remapping for logic circuits L Benini, P Vuillod, G De Micheli IEEE transactions on computer-aided design of integrated circuits and …, 1998 | 13 | 1998 |
| Scalable Boolean methods in a modern synthesis flow E Testa, L Amarú, M Soeken, A Mishchenko, P Vuillod, J Luo, C Casares, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 12 | 2019 |
| Re-mapping for low power under tight timing constraints P Vuillod, L Benini, G De Micheli Proceedings of the 1997 international symposium on Low power electronics and …, 1997 | 12 | 1997 |
| Extending boolean methods for scalable logic synthesis E Testa, L Amaru, M Soeken, A Mishchenko, P Vuillod, PE Gaillardon, ... IEEE Access 8, 226828-226844, 2020 | 11 | 2020 |
| SAT-sweeping enhanced for logic synthesis L Amarú, F Marranghello, E Testa, C Casares, V Possani, J Luo, P Vuillod, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 9 | 2020 |
| Delay optimization during circuit design at layout level P Vuillod, JC Madre US Patent 8,549,448, 2013 | 9 | 2013 |
| LUT-based optimization for ASIC design flow L Amarú, V Possani, E Testa, F Marranghello, C Casares, J Luo, P Vuillod, ... 2021 58th ACM/IEEE Design Automation Conference (DAC), 871-876, 2021 | 7 | 2021 |
| Synthesis of low-power partially-clocked systems from high-level specifications L Benini, P Vuillod, C Coelho, G De Micheli 9th International Symposium on System Synthesis, 1996 | 6 | 1996 |
| Majority-based design flow for AQFP superconducting family G Meuli, V Possani, R Singh, SY Lee, AT Calvino, DS Marakkalage, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 34-39, 2022 | 5 | 2022 |
| Multi-level logic benchmarks: An exactness study L Amarú, M Soeken, W Haaswijk, E Testa, P Vuillod, J Luo, PE Gaillardon, ... 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 157-162, 2017 | 5 | 2017 |
| Improving LUT-based optimization for ASICs WL Neto, L Amarú, V Possani, P Vuillod, J Luo, A Mishchenko, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 421-426, 2022 | 4 | 2022 |
| Generalized matching from theory to application P Vuillod, L Benini, G De Micheli IEEE INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, 13-21, 1997 | 4 | 1997 |
| Integrated circuit (IC) optimization using Boolean resynthesis LG Amaru, P Vuillod, J Luo US Patent 10,740,517, 2020 | 3 | 2020 |
| Integrated ESOP refactoring for industrial designs W Haaswijk, LG Amaru, P Vuillod, J Luo, M Soeken, G De Micheli 2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018 | 3 | 2018 |
