Variability sources in nanoscale bulk FinFETs and TiTaN-a promising low variability WFM for 7/5nm CMOS nodes MS Bhoir, T Chiarella, LÅ Ragnarsson, J Mitard, N Horiguchi, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.2. 1-36.2. 4, 2019
14 2019 Source Underlap—A Novel Technique to Improve Safe Operating Area and Output-Conductance in LDMOS Transistors MS Bhoir, KN Kaushal, SR Panda, AK Singh, HS Jatana, NR Mohapatra
IEEE Transactions on Electron Devices 66 (11), 4823-4828, 2019
10 2019 Effects of scaling on analog FoMs of UTBB FD-SOI MOS transistors: a detailed analysis MS Bhoir, NR Mohapatra
IEEE Transactions on Electron Devices 67 (8), 3035-3041, 2020
9 2020 Predictive effective mobility model for FDSOI transistors using technology parameters P Kushwaha, H Agarwal, YS Chauhan, M Bhoir, NR Mohapatra, ...
2016 IEEE International Conference on Electron Devices and Solid-State …, 2016
8 2016 Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis MS Bhoir, T Chiarella, LÅ Ragnarsson, J Mitard, V Terzeiva, N Horiguchi, ...
IEEE Journal of the Electron Devices Society 7, 1217-1224, 2019
6 2019 Split-gate architecture for higher breakdown voltage in STI based LDMOS transistors S Teja, M Bhoir, NR Mohapatra
2017 International Conference on Electron Devices and Solid-State Circuits …, 2017
5 2017 Back-Gate Bias and Substrate Doping Influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines MS Bhoir, YS Chauhan, NR Mohapatra
IEEE Transactions on Electron Devices 66 (2), 861-867, 2019
4 2019 Impact of substrate on the frequency behavior of trans-conductance in ultrathin body and BOX FDSOI MOS devices-a physical insight M Bhoir, P Kushwaha, YS Chauhan, NR Mohapatra
2017 International Symposium on VLSI Technology, Systems and Application …, 2017
4 2017 Impact of BOX thickness and ground-plane on non-linearity of UTBB FD-SOI MOS transistors MS Bhoir, NR Mohapatra
2018 Joint International EUROSOI Workshop and International Conference on …, 2018
3 2018 Process-induced MS Bhoir, T Chiarella, LÅ Ragnarsson, J Mitard, N Horiguchi, ...
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020
2 2020 Effect of Sub-10nm Fin-widths on the Analog Performance of FinFETs MS Bhoir, NR Mohapatra, T Chiarella, LÅ Ragnarsson, J Mitard, ...
2019 Electron Devices Technology and Manufacturing Conference (EDTM), 7-9, 2019
2 2019 Physics-based parameter extraction methodology for channel doping gradient (CDG) LDMOS transistors based on HiSIM-HV2 model S Patil, KN Kaushal, MS Bhoir, NR Mohapatra
2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2021
2021 V ₜ Extraction Methodologies Influence Process Induced V ₜ Variability: Does This Fact Still Hold for Advanced Technology Nodes?MS Bhoir, T Chiarella, J Mitard, N Horiguchi, NR Mohapatra
IEEE Transactions on Electron Devices 67 (11), 4691-4695, 2020
2020 Advanced CMOS technologies for SoC applications: challenges and solutions from Analog/RF perspective MS Bhoir
Indian Institute of Technology Gandhinagar, 2020
2020 Design of complementary high-voltage device compatible with SCL's 0.18um CMOS technology MS Bhoir
Indian Institute of Technology Gandhinagar, 2015
2015 
Lars-Åke RagnarssonimecAdresse e-mail validée de imec.be
