| 33.4 A 28nm 2Mb STT-MRAM computing-in-memory macro with a refined bit-cell and 22.4-41.5 TOPS/W for AI inference H Cai, Z Bian, Y Hou, Y Zhou, Y Guo, X Tian, B Liu, X Si, Z Wang, J Yang, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 500-502, 2023 | 19 | 2023 |
| Commodity bit-cell sponsored MRAM interaction design for binary neural network H Cai, Z Bian, Z Fan, B Liu, L Naviner IEEE Transactions on Electron Devices 69 (4), 1721-1726, 2021 | 7 | 2021 |
| Investigation of PVT-aware STT-MRAM sensing circuits for low-VDD scenario Z Bian, X Hong, Y Guo, L Naviner, W Ge, H Cai Micromachines 12 (5), 551, 2021 | 6 | 2021 |
| In-MRAM computing elements with single-step convolution and fully connected for BNN/TNN ZJ Bian, Y Guo, B Liu, H Cai 2021 IEEE International Conference on Integrated Circuits, Technologies and …, 2021 | 2 | 2021 |
| Computing in-memory with cascaded spintronic devices for AI edge Z Bian, B Liu, H Cai Computers and Electrical Engineering 109, 108767, 2023 | 1 | 2023 |
| Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming X Tian, Z Bian, H Cai 2022 IEEE International Conference on Integrated Circuits, Technologies and …, 2022 | | 2022 |
| Modified Peripheral MRAM Sensing for In-memory Boolean Logic ZJ Bian, X Hong, J Chen, H Cai 2021 IEEE 14th International Conference on ASIC (ASICON), 1-4, 2021 | | 2021 |
