A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration Q Huang, R Huang, Z Zhan, Y Qiu, W Jiang, C Wu, Y Wang
2012 International Electron Devices Meeting, 8.5. 1-8.5. 4, 2012
138 2012 A comparative study on the impacts of interface traps on tunneling FET and MOSFET Y Qiu, R Wang, Q Huang, R Huang
IEEE Transactions on Electron Devices 61 (5), 1284-1291, 2014
121 2014 An analytical surface potential model accounting for the dual-modulation effects in tunnel FETs C Wu, R Huang, Q Huang, C Wang, J Wang, Y Wang
IEEE Transactions on Electron Devices 61 (8), 2690-2696, 2014
92 2014 A novel tunnel FET design with stacked source configuration for average subthreshold swing reduction C Wu, Q Huang, Y Zhao, J Wang, Y Wang, R Huang
IEEE Transactions on Electron Devices 63 (12), 5072-5076, 2016
63 2016 New insights into the physical origin of negative capacitance and hysteresis in NCFETs H Wang, M Yang, Q Huang, K Zhu, Y Zhao, Z Liang, C Chen, Z Wang, ...
2018 IEEE International Electron Devices Meeting (IEDM), 31.1. 1-31.1. 4, 2018
57 2018 Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective Q Huang, R Huang, C Wu, H Zhu, C Chen, J Wang, L Guo, R Wang, L Ye, ...
2014 IEEE International Electron Devices Meeting, 13.3. 1-13.3. 4, 2014
54 2014 Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold slope and high ION /IOFF by gate configuration and barrier modulation Q Huang, Z Zhan, R Huang, X Mao, L Zhang, Y Qiu, Y Wang
2011 International Electron Devices Meeting, 16.2. 1-16.2. 4, 2011
54 2011 Bio-inspired neurons based on novel leaky-FeFET with ultra-low hardware cost and advanced functionality for all-ferroelectric neural network C Chen, M Yang, S Liu, T Liu, K Zhu, Y Zhao, H Wang, Q Huang, R Huang
2019 symposium on VLSI technology, T136-T137, 2019
53 2019 Capacitor-less stochastic leaky-FeFET neuron of both excitatory and inhibitory connections for SNN with reduced hardware cost J Luo, L Yu, T Liu, M Yang, Z Fu, Z Liang, L Chen, C Chen, S Liu, S Wu, ...
2019 IEEE International Electron Devices Meeting (IEDM), 6.4. 1-6.4. 4, 2019
51 2019 Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling C Wang, CL Wu, JX Wang, QQ Huang, R Huang
Science China. Information Sciences 58 (2), 1-8, 2015
51 2015 Artificial Neural Network Based on Doped HfO2 Ferroelectric Capacitors With Multilevel Characteristics Q Zheng, Z Wang, N Gong, Z Yu, C Chen, Y Cai, Q Huang, H Jiang, Q Xia, ...
IEEE Electron Device Letters 40 (8), 1309-1312, 2019
46 2019 Vertical WS2 /SnS2 van der Waals Heterostructure for Tunneling Transistors J Wang, R Jia, Q Huang, C Pan, J Zhu, H Wang, C Chen, Y Zhang, ...
Scientific reports 8 (1), 17755, 2018
43 2018 A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High Y Zhao, C Wu, Q Huang, C Chen, J Zhu, L Guo, R Jia, Z Lv, Y Yang, M Li, ...
IEEE Electron Device Letters 38 (5), 540-543, 2017
40 2017 First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap Q Huang, R Jia, C Chen, H Zhu, L Guo, J Wang, J Wang, C Wu, R Wang, ...
2015 IEEE International Electron Devices Meeting (IEDM), 22.2. 1-22.2. 4, 2015
37 2015 Design guideline for complementary heterostructure tunnel FETs with steep slope and improved output behavior C Wu, R Huang, Q Huang, J Wang, Y Wang
IEEE Electron Device Letters 37 (1), 20-23, 2015
33 2015 Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High J Zhu, Y Zhao, Q Huang, C Chen, C Wu, R Jia, R Huang
IEEE Electron Device Letters 38 (9), 1200-1203, 2017
32 2017 A novel negative capacitance tunnel FET with improved subthreshold swing and nearly non-hysteresis through hybrid modulation Y Zhao, Z Liang, Q Huang, C Chen, M Yang, Z Sun, K Zhu, H Wang, S Liu, ...
IEEE electron device letters 40 (6), 989-992, 2019
28 2019 New-generation design-technology co-optimization (DTCO): Machine-learning assisted modeling framework Z Zhang, R Wang, C Chen, Q Huang, Y Wang, C Hu, D Wu, J Wang, ...
2019 Silicon Nanoelectronics Workshop (SNW), 1-2, 2019
27 2019 Resistive-gate field-effect transistor: A novel steep-slope device based on a metal—Insulator—Metal—Oxide gate stack Q Huang, R Huang, Y Pan, S Tan, Y Wang
IEEE Electron Device Letters 35 (8), 877-879, 2014
26 2014 Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering Q Huang, R Huang, C Chen, C Wu, J Wang, C Wang, Y Wang
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
26 2014 
Jibin ZouPh.D. graduate of Peking UniversityAdresse e-mail validée de pku.edu.cn
