Tanguy Risset
Tanguy Risset
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Construction of do loops from systems of affine constraints
JF Collard, T Risset, P Feautrier
Parallel Processing Letters 5 (03), 421-436, 1995
(Pen)-ultimate tiling?
P Boulet, A Darte, T Risset, Y Robert
Integration 17 (1), 33-51, 1994
Software defined radio architecture survey for cognitive testbeds
M Dardaillon, K Marquet, T Risset, A Scherrer
2012 8th international wireless communications and mobile computing …, 2012
Sytare: A lightweight kernel for NVRAM-based transiently-powered systems
G Berthou, T Delizy, K Marquet, T Risset, G Salagnac
IEEE Transactions on Computers 68 (9), 1390-1403, 2018
Loop nest scheduling and transformations
A Darte, T Risset, Y Robert
Environments and Tools for Parallel Scientific Computing 6, 309-332, 1993
On manipulating Z-polyhedra using a canonical representation
P Quinton, S Rajopadhye, T Risset
Parallel Processing Letters 7 (02), 181-194, 1997
Resource-constrained scheduling of partitioned algorithms on processor arrays
M Dion, T Risset, Y Robert
Integration 20 (2), 139-159, 1996
Hardware synthesis for multi-dimensional time
AC Guillou, P Quinton, T Risset
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
On manipulating Z-polyhedra
P Quinton, S Rajopadhye, T Risset
IRISA, 1996
Precise tiling for uniform loop nests
PY Calland, T Risset
Proceedings The International Conference on Application Specific Array …, 1995
Structuration of the alpha language
F de Dinechin, P Quinton, T Risset
Programming models for massively parallel computers, 18-24, 1995
Long-range dependence and on-chip processor traffic
A Scherrer, A Fraboulet, T Risset
Microprocessors and microsystems 33 (1), 72-80, 2009
Automatic phase detection for stochastic on-chip traffic generation
A Scherrer, A Fraboulet, T Risset
Proceedings of the 4th international conference on Hardware/software …, 2006
Peripheral state persistence for transiently-powered systems
G Berthou, T Delizy, K Marquet, T Risset, G Salagnac
2017 Global Internet of Things Summit (GIoTS), 1-6, 2017
CorteXlab: An open FPGA-based facility for testing SDR & cognitive radio networks in a reproducible environment
A Massouri, L Cardoso, B Guillon, F Hutu, G Villemaud, T Risset, ...
2014 IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS …, 2014
A library for Z-polyhedral operations
SPK Nookala, T Risset
IRISA, 2000
Generating regular arithmetic circuits with AlpHard
P Le Moenner, L Perraudeau, P Quinton, S Rajopadhye, T Risset
Publication interne- IRISA, 1996
Full duplex prototype of OFDM on GNURadio and USRPs
W Zhou, G Villemaud, T Risset
2014 IEEE Radio and Wireless Symposium (RWS), 217-219, 2014
Hardware design methodology with the Alpha language
AC Guillou, F Quilleré, P Quinton, S Rajopadhye, T Risset
FDL’01, 2001
Synthesis of processor arrays for the algebraic path problem: unifying old results and deriving new architectures
T Risset, Y Robert
Parallel Processing Letters 1 (01), 19-28, 1991
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