| A 30-MHz voltage-mode buck converter using delay-line-based PWM control Q Huang, C Zhan, J Burm IEEE Transactions on Circuits and Systems II: Express Briefs 65 (11), 1659-1663, 2017 | 24 | 2017 |
| Analysis and design of a current-mode bandgap reference with high power supply ripple rejection L Wang, C Zhan, J Tang, S Zhao, G Cai, Y Liu, Q Huang, G Li Microelectronics journal 68, 7-13, 2017 | 24 | 2017 |
| An energy-efficient frequency-domain CMOS temperature sensor with switched vernier time-to-digital conversion Q Huang, H Joo, J Kim, C Zhan, J Burm IEEE Sensors Journal 17 (10), 3001-3011, 2017 | 24 | 2017 |
| A− 40° C to 120° C, 169 ppm/° C nano-ampere CMOS current reference Q Huang, C Zhan, L Wang, Z Li, Q Pan IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1494-1498, 2020 | 15 | 2020 |
| A 4-MHz digitally controlled voltage-mode buck converter with embedded transient improvement using delay line control techniques Q Huang, C Zhan, J Burm IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 4029-4040, 2020 | 11 | 2020 |
| Design of high-PSRR current-mode bandgap reference with improved frequency compensation L Wang, C Zhan, S Zhao, G Cai, Y Liu, Q Huang, G Li 2016 IEEE International Conference on Electron Devices and Solid-State …, 2016 | 11 | 2016 |
| A low-complexity fast-locking digital PLL with multi-output bang-bang phase detector Q Huang, C Zhan, J Burm 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 418-420, 2016 | 6 | 2016 |
| A 56-Gb/s PAM4 continuous-time linear equalizer with fixed peaking frequency in 40-nm CMOS M Tang, Z Li, J Hu, Q Huang, N Qi, H Yu, Q Pan 2019 IEEE International Conference on Integrated Circuits, Technologies and …, 2019 | 5 | 2019 |
| Two CMOS time to digital converters using successive approximation register logic H Park, Q Huang, C Yu, S Kim, G Ahn, J Burm IEICE Electronics Express 15 (22), 20180840-20180840, 2018 | 3 | 2018 |
| An 18-Gb/s PRBS Generator in 40-nm CMOS J Hu, Z Zhani, Q Huang, J Yang, M Hu, Q Jiang, Y Guo, Q Pan 2020 International Conference on Electronics, Information, and Communication …, 2020 | 2 | 2020 |
| A low-complexity locking-accelerated digital PLL with multi-output bang-bang phase detector Q Huang, C Zhan, J Burm Microelectronics journal 67, 19-24, 2017 | 2 | 2017 |
| A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme W Xiao, Q Huang, H Mosalam, C Zhan, Z Li, Q Pan IEEE Transactions on Circuits and Systems I: Regular Papers 69 (2), 634-644, 2021 | 1 | 2021 |
| All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector C Yu, H Park, Q Huang, D Lee, H Kim, H Lee, J Burm IEICE Electronics Express 17 (6), 20200024-20200024, 2020 | 1 | 2020 |
| A 56-gb/s pam4 variable gain amplifier in 40-nm cmos technology Z Li, M Tang, Y Guo, Q Huang, Q Pan 2019 IEEE International Conference on Electron Devices and Solid-State …, 2019 | 1 | 2019 |
| High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs J Lee, Q Huang, K Kim, K Kim, J Burm JSTS: Journal of Semiconductor Technology and Science 15 (1), 22-28, 2015 | 1 | 2015 |
| Clock data recovery circuit and clock data recovery method Q Pan, X Wenbo, Q Huang, J Yang, D Xuewei, Y Hao US Patent App. 18/279,895, 2024 | | 2024 |
Chenchang ZhanAssociate Professor, SUSTechVerified email at ieee.org
