Theodore S. Moise
Theodore S. Moise
Adresse e-mail validée de ti.com
Titre
Citée par
Citée par
Année
Hardmask designs for dry etching FeRAM capacitor stacks
T Moise, SR Gilbert, SR Summerfelt, G Xing, L Colombo
US Patent 6,534,809, 2003
3182003
A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter
TPE Broekaert, B Brar, JPA van der Wagt, AC Seabaugh, FJ Morris, ...
IEEE Journal of Solid-State Circuits 33 (9), 1342-1349, 1998
2501998
Integrated circuit and method
TS Moise, G Xing, M Visokay, JF Gaynor, SR Gilbert, F Celii, ...
US Patent 6,211,035, 2001
2432001
Integrated circuit and method
TS Moise, G Xing, M Visokay, JF Gaynor, SR Gilbert, F Celii, ...
US Patent 6,211,035, 2001
2432001
Integrated circuit and method
TS Moise, G Xing, M Visokay, JF Gaynor, SR Gilbert, F Celii, ...
US Patent 6,211,035, 2001
2432001
A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter
TPE Broekaert, B Brar, JPA van der Wagt, AC Seabaugh, FJ Morris, ...
IEEE Journal of Solid-State Circuits 33 (9), 1342-1349, 1998
2391998
Quantitative simulation of a resonant tunneling diode
RC Bowen, G Klimeck, RK Lake, WR Frensley, T Moise
Journal of applied physics 81 (7), 3207-3213, 1997
1831997
Quantitative simulation of a resonant tunneling diode
RC Bowen, G Klimeck, RK Lake, WR Frensley, T Moise
Journal of applied physics 81 (7), 3207-3213, 1997
1831997
Quantum device simulation with a generalized tunneling formula
G Klimeck, R Lake, RC Bowen, WR Frensley, TS Moise
Applied physics letters 67 (17), 2539-2541, 1995
1601995
Integrated circuit and method
TS Moise, G Xing, M Visokay, JF Gaynor, SR Gilbert, F Celii, ...
US Patent 6,444,542, 2002
1092002
A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process
HP McAdams, R Acklin, T Blake, XH Du, J Eliason, J Fong, WF Kraus, ...
IEEE Journal of Solid-State Circuits 39 (4), 667-677, 2004
962004
Sputtering process for the conformal deposition of a metallization or insulating layer
PC Van Buskirk, MW Russell, DJ Vestyck, SR Summerfelt, TS Moise
US Patent 6,100,200, 2000
902000
SOC CMOS technology for personal internet products
D Buss, BL Evans, J Bellay, W Krenik, B Haroun, D Leipold, K Maggio, ...
IEEE Transactions on Electron Devices 50 (3), 546-556, 2003
692003
Protection of tungsten alignment mark for FeRAM processing
SR Summerfelt, L Colombo, SR Gilbert, TS Moise IV, S Aggarwal
US Patent 6,528,386, 2003
68*2003
Magnitude, origin, and evolution of piezoelectric optical nonlinearities in strained [111] B InGaAs/GaAs quantum wells
AN Cartwright, DS McCallum, TF Boggess, AL Smirl, TS Moise, LJ Guido, ...
Journal of applied physics 73 (11), 7767-7774, 1993
621993
Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process
TS Moise, SR Summerfelt, H McAdams, S Aggarwal, KR Udayakumar, ...
Digest. International Electron Devices Meeting,, 535-538, 2002
612002
Reliability properties of low-voltage ferroelectric capacitors and memory arrays
JA Rodriguez, K Remack, K Boku, KR Udayakumar, S Aggarwal, ...
IEEE Transactions on Device and Materials Reliability 4 (3), 436-449, 2004
582004
Preparation of thin films by metalorganic chemical vapor deposition for low voltage ferroelectric memory
SR Gilbert, S Hunter, D Ritchey, C Chi, DV Taylor, J Amano, S Aggarwal, ...
Journal of applied physics 93 (3), 1713-1717, 2003
562003
Method of forming an FeRAM having a multi-layer hard mask and patterning thereof
SR Summerfelt, S Aggarwal, L Colombo, TS Moise IV, JS Martin
US Patent 6,828,161, 2004
542004
Fabricating an embedded ferroelectric memory cell
T Moise, S Summerfelt, E Zielinski, S Johnson
US Patent 6,734,477, 2004
542004
Le système ne peut pas réaliser cette opération maintenant. Veuillez réessayer plus tard.
Articles 1–20