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Xiaoyao Liang
Xiaoyao Liang
Shanghai Jiao Tong University
Adresse e-mail validée de eecs.harvard.edu - Page d'accueil
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Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar
L Chen, J Li, Y Chen, Q Deng, J Shen, X Liang, L Jiang
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 19-24, 2017
1982017
Mitigating the impact of process variations on processor register files and execution units
X Liang, D Brooks
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
1662006
Process variation tolerant 3T1D-based cache architectures
X Liang, R Canal, GY Wei, D Brooks
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
1352007
Revival: A variation-tolerant architecture using voltage interpolation and variable latency
X Liang, GY Wei, D Brooks
ACM SIGARCH Computer Architecture News 36 (3), 191-202, 2008
972008
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
N Jing, Y Shen, Y Lu, S Ganapathy, Z Mao, M Guo, R Canal, X Liang
ACM SIGARCH Computer Architecture News 41 (3), 344-355, 2013
852013
Agileregulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture
G Yan, Y Li, Y Han, X Li, M Guo, X Liang
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
702012
Towards sustainable in-situ server systems in the big data era
C Li, Y Hu, L Liu, J Gu, M Song, X Liang, J Yuan, T Li
Acm Sigarch Computer Architecture News 43 (3S), 14-26, 2015
672015
Drq: dynamic region-based quantization for deep neural network acceleration
Z Song, B Fu, F Wu, Z Jiang, L Jiang, N Jing, X Liang
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
552020
Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability
X Liang, R Canal, GY Wei, D Brooks
IEEE micro 28 (1), 60-68, 2008
532008
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
X Liang, K Turgay, D Brooks
2007 IEEE/ACM International Conference on Computer-Aided Design, 824-830, 2007
522007
Revival: A variation-tolerant architecture using voltage interpolation and variable latency
X Liang, GY Wei, D Brooks
IEEE micro 29 (1), 127-138, 2009
482009
Power attack defense: Securing battery-backed data centers
C Li, Z Wang, X Hou, H Chen, X Liang, M Guo
ACM SIGARCH Computer Architecture News 44 (3), 493-505, 2016
462016
System-level hardware failure prediction using deep learning
X Sun, K Chakrabarty, R Huang, Y Chen, B Zhao, H Cao, Y Han, X Liang, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
432019
Microarchitecture parameter selection to optimize system performance under process variation
X Liang, D Brooks
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006
392006
Efficient graph computation on hybrid CPU and GPU systems
T Zhang, J Zhang, W Shu, MY Wu, X Liang
The Journal of Supercomputing 71, 1563-1586, 2015
352015
Empirical performance models for 3T1D memories
K Lovin, BC Lee, X Liang, D Brooks, GY Wei
2009 IEEE International Conference on Computer Design, 398-403, 2009
352009
Compiler assisted dynamic register file in GPGPU
N Jing, H Liu, Y Lu, X Liang
International Symposium on Low Power Electronics and Design (ISLPED), 3-8, 2013
342013
A process-variation-tolerant floating-point unit with voltage interpolation and variable latency
X Liang, D Brooks, GY Wei
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
262008
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
N Jing, J Wang, F Fan, W Yu, L Jiang, C Li, X Liang
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
252016
Energy-efficient eDRAM-based on-chip storage architecture for GPGPUs
N Jing, L Jiang, T Zhang, C Li, F Fan, X Liang
IEEE Transactions on Computers 65 (1), 122-135, 2015
252015
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