Design and analysis of millimeter-wave digitally controlled oscillators with C-2C exponentially scaling switched-capacitor ladder Z Huang, HC Luong
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (6), 1299-1307, 2017
39 2017 2.3 A 4.2 µs-settling-time 3rd-order 2.1 GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL Z Huang, B Jiang, L Li, HC Luong
2016 IEEE International Solid-State Circuits Conference (ISSCC), 40-41, 2016
30 2016 An 82–107.6-GHz Integer- ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta … Z Huang, HC Luong
IEEE Journal of Solid-State Circuits 54 (2), 358-367, 2018
25 2018 25.6 A 70.5-to-85.5 GHz 65nm phase-locked loop with passive scaling of loop filter Z Huang, HC Luong, B Chi, Z Wang, H Jia
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
23 2015 A 2.1-GHz third-order cascaded PLL with sub-sampling DLL and clock-skew-sampling phase detector Z Huang, B Jiang, HC Luong
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (7), 2118-2126, 2017
15 2017 Magnetic-tuning millimeter-wave CMOS oscillators X Liu, Z Huang, J Yin, HC Luong
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2019
13 2019 A dithering-less 54.79-to-63.16 GHz DCO with 4-Hz frequency resolution using an exponentially-scaling C-2C switched-capacitor ladder Z Huang, HC Luong
2015 Symposium on VLSI Circuits (VLSI Circuits), C234-C235, 2015
12 2015 An 82-to-108GHz −181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma … Z Huang, HC Luong
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 260-262, 2018
11 2018 Exponentially scaling switched capacitor HC Luong, Z Huang
US Patent 9,912,320, 2018
3 2018 Magnetic-Tuning Millimeter X Liu, Z Huang, J Yin, HC Luong
2019 Exponentially scaling switched capacitor HC Luong, Z Huang
2018