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Portal Jean-Michel
Portal Jean-Michel
Full Professor Aix-Marseille Université - IM2NP
Adresse e-mail validée de univ-amu.fr
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Testing the interconnect of RAM-based FPGAs
M Renovell, JM Portal, J Figueras, Y Zorian
IEEE Design & Test of Computers 15 (1), 45-50, 1998
2181998
Robust compact model for bipolar oxide-based resistive switching memories
M Bocquet, D Deleruyelle, H Aziza, C Muller, JM Portal, T Cabout, ...
IEEE transactions on electron devices 61 (3), 674-681, 2014
1442014
Synchronous non-volatile logic gate design based on resistive switching memories
W Zhao, M Moreau, E Deng, Y Zhang, JM Portal, JO Klein, M Bocquet, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (2), 443-454, 2013
1212013
EEPROM memory: Threshold voltage built in self diagnosis
JM Portal, H Aziza
International Test Conference, 2003. Proceedings. ITC 2003., 23-23, 2003
1032003
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks
M Bocquet, T Hirztlin, JO Klein, E Nowak, E Vianello, JM Portal, ...
2018 IEEE International Electron Devices Meeting (IEDM), 20.6. 1-20.6. 4, 2018
922018
Definition of an innovative filling structure for digital blocks: the DFM filler cell
L Remy, P Coll, F Picot, P Mico, JM Portal
2009 16th IEEE International Conference on Electronics, Circuits and Systems …, 2009
892009
EEPROM diagnosis based on threshold voltage embedded measurement
JM Portal, H Aziza, D Née
Journal of Electronic Testing 21, 33-42, 2005
882005
Self-consistent physical modeling of set/reset operations in unipolar resistive-switching memories
M Bocquet, D Deleruyelle, C Muller, JM Portal
Applied Physics Letters 98 (26), 2011
752011
Digital biologically plausible implementation of binarized neural networks with differential hafnium oxide resistive memory arrays
T Hirtzlin, M Bocquet, B Penkovsky, JO Klein, E Nowak, E Vianello, ...
Frontiers in neuroscience 13, 1383, 2020
722020
SRAM-based FPGA's: testing the LUT/RAM modules
M Renovell, JM Portal, J Figueras, Y Zorian
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
681998
IS-FPGA: a new symmetric FPGA architecture with implicit scan
M Renovell, P Faure, JM Portal, J Figueras, Y Zorian
Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 924-931, 2001
662001
RRAM-based FPGA for" Normally off, Instantly on" Applications
O Turkyilmaz, S Onkaraiah, M Reyboz, F Clermidy, Hraziia, C Anghel, ...
Proceedings of the 2012 IEEE/ACM international symposium on nanoscale …, 2012
552012
Outstanding bit error tolerance of resistive RAM-based binarized neural networks
T Hirtzlin, M Bocquet, JO Klein, E Nowak, E Vianello, JM Portal, ...
2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019
502019
High-density 3D monolithically integrated multiple 1T1R multi-level-cell for neural networks
E Esmanhotto, L Brunet, N Castellani, D Bonnet, T Dalgaty, L Grenouillet, ...
2020 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2020
482020
Bipolar ReRAM based non-volatile flip-flops for low-power architectures
S Onkaraiah, M Reyboz, F Clermidy, JM Portal, M Bocquet, C Muller, ...
10th IEEE International NEWCAS Conference, 417-420, 2012
482012
Minimizing the number of test configurations for different FPGA families
M Renovell, JM Portal, J Figuras, Y Zorian
Proceedings Eighth Asian Test Symposium (ATS'99), 363-368, 1999
481999
Stochastic computing for hardware implementation of binarized neural networks
T Hirtzlin, B Penkovsky, M Bocquet, JO Klein, JM Portal, D Querlioz
IEEE Access 7, 76394-76403, 2019
472019
Compact modeling solutions for oxide-based resistive switching memories (OxRAM)
M Bocquet, H Aziza, W Zhao, Y Zhang, S Onkaraiah, C Muller, M Reyboz, ...
Journal of Low Power Electronics and Applications 4 (1), 1-14, 2014
472014
Test pattern and test configuration generation methodology for the logic of RAM-based FPGA
M Renovell, JM Portal, J Figueras, Y Zorian
Proceedings Sixth Asian Test Symposium (ATS'97), 254-259, 1997
441997
RAM-based FPGAs: A test approach for the configurable logic
M Renovell, JM Portal, J Figueras, Y Zorian
Proceedings Design, Automation and Test in Europe, 82-88, 1998
421998
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