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Adel Ejjeh
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HPVM2FPGA: Enabling true hardware-agnostic FPGA programming
A Ejjeh, L Medvinsky, A Councilman, H Nehra, S Sharma, V Adve, L Nardi, ...
2022 IEEE 33rd International Conference on Application-specific Systems …, 2022
32022
Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration
G Zacharopoulos, A Ejjeh, Y Jing, EY Yang, T Jia, I Brumar, J Intan, ...
arXiv preprint arXiv:2201.08603, 2022
22022
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL
A Ejjeh, V Adve, R Rutenbar
arXiv preprint arXiv:2201.03558, 2022
22022
HPVM: Hardware-Agnostic Programming for Heterogeneous Parallel Systems
A Ejjeh, A Councilman, A Kothari, M Kotsifakou, L Medvinsky, AR Noor, ...
IEEE Micro 42 (5), 108-117, 2022
2022
Architecture performance simulator for the disjoint out-of-order execution processor (DOE) and the OpenDOE API
AJ Ejjeh
Theses, Dissertations, and Projects, 2015
2015
Haase, Julian 156 Haering, Tim 139 Hao, Cong 11, 131 Hepola, Kari 161
D Abts, V Adve, R Agrawal, I Ahmed, MAZ Alves, R Andri, LS Araújo, ...
Simplifying High Level Synthesis through Compiler Techniques
A Ejjeh, V Adve, S Adve, L Carloni, R Rutenbar
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