Modification of electrical properties of Au/n-type InP Schottky diode with a high-k Ba 0.6 Sr 0.4 TiO 3 interlayer PP Thapaswini, R Padma, N Balaram, B Bindu, VR Reddy Superlattices and Microstructures 93, 82-91, 2016 | 36 | 2016 |
Analytical model of drain current of Si/SiGe heterostructure p-channel MOSFETs for circuit simulation B Bindu, N DasGupta, A DasGupta IEEE Transactions on Electron Devices 53 (6), 1411-1419, 2006 | 21 | 2006 |
A unified model for gate capacitance–voltage characteristics and extraction of parameters of Si/SiGe heterostructure pMOSFETs B Bindu, N DasGupta, A DasGupta IEEE Transactions on Electron Devices 54 (8), 1889-1896, 2007 | 20 | 2007 |
Dual-Summed Flipped Voltage Follower LDO Regulator with Active Feed-Forward Compensation P Manikandan, B Bindu AEU-International Journal of Electronics and Communications 123 (8), 153314, 2020 | 19 | 2020 |
An Analytical Model of Single-Event Transients in Double-Gate MOSFET for Circuit Simulation YM Aneesh, SR Sriram, KR Pasupathy, B Bindu IEEE Transactions on Electron Devices 66 (9), 3710-3717, 2019 | 17 | 2019 |
Analytical solution of the switching trap model for negative bias temperature stress B Bindu, W Goes, B Kaczer, T Grasser Integrated Reliability Workshop, 2009. IRW'09. IEEE International, 93-96, 2009 | 16 | 2009 |
A Physics-based Single Event Transient Pulse Width Model for CMOS VLSI Circuits YM Aneesh, B Bindu IEEE Transactions on Device and Materials Reliability 20 (4), 723 - 730, 2020 | 15 | 2020 |
A Review on Circuit Simulation Techniques of Single-Event Transients and their Propagation in Delay Locked Loop KR Pasupathy, B Bindu IETE Technical Review 34 (3), Pages 276-285, 2017 | 15 | 2017 |
Analytical model of drain current of strained-Si/strained-Si 1− Y Ge Y/relaxed-Si 1− X Ge X NMOSFETs and PMOSFETs for circuit simulation B Bindu, N DasGupta, A DasGupta Solid-state electronics 50 (3), 448-455, 2006 | 14 | 2006 |
Low power, high speed carbon nanotube FET based level shifters for multi-V DD Systems-On-Chips KR Pasupathy, B Bindu Microelectronics Journal 46 (12), 1269-1274, 2015 | 13 | 2015 |
Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction B Bindu, B Cheng, G Roy, X Wang, S Roy, A Asenov Solid-State Electronics 54 (3), 307-315, 2010 | 13 | 2010 |
A transient enhanced cap-less low-dropout regulator for wide range of load currents and capacitances P Manikandan, B Bindu Microelectronics Journal 115, 105207, 2021 | 11 | 2021 |
High PSR Capacitor-Less LDO with Adaptive Circuit for Varying Loads P Manikandan, B Bindu Journal of Circuits, Systems and Computers 29 (11), 2050178:1-12, 2020 | 10 | 2020 |
Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation SR Sriram, B Bindu Journal of Computational Electronics 17 (1), 163-171, 2018 | 9 | 2018 |
A Physics-Based Model of Double-Gate Tunnel FET for Circuit Simulation A Narendiran, K Akhila, B Bindu IETE Journal of Research 62 (3), 387-393, 2016 | 9 | 2016 |
Impact of NBTI induced variations on delay locked loop multi-phase clock generator SR Sriram, B Bindu Microelectronics Reliability 60 (5), 33-40, 2016 | 9 | 2016 |
Analysis of bipolar amplification due to heavy-ion irradiation in 45 nm FDSOI MOSFET with thin BOX and ground plane KR Pasupathy, B Bindu Microelectronics Reliability (elsevier) 98, 56-62, 2019 | 8 | 2019 |
A physics-based 3-D potential and threshold voltage model for undoped triple-gate FinFET with interface trapped charges SR Sriram, B Bindu Journal of Computational Electronics (springer) 18 (1), 37-45, 2019 | 8 | 2019 |
A push-pulled capacitor-less FVF LDO with active feed-forward compensator P Manikandan, B Bindu International Journal of Electronics 108 (4), 684–704, 2021 | 6 | 2021 |
A physics-based model for LER-induced threshold voltage variations in double-gate MOSFET SR Sriram, B Bindu Journal of Computational Electronics 19 (2), 622–630, 2020 | 6 | 2020 |