| Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs A Lahgere, M Panchore, J Singh Superlattices and Microstructures 96, 16-25, 2016 | 37 | 2016 |
| Low power and high speed CMOS comparator design using 0.18 μm technology M Panchore, RS Gamad International Journal of Electronic Engineering Research 2 (1), 71-77, 2010 | 37 | 2010 |
| Impact of channel hot carrier effect in junction-and doping-free devices and circuits M Panchore, J Singh, SP Mohanty IEEE Transactions on Electron Devices 63 (12), 5068-5071, 2016 | 27 | 2016 |
| 3-D simulation of junction-and doping-free field-effect transistor under heavy ion irradiation N Kamal, M Panchore, J Singh IEEE Transactions on Device and Materials Reliability 18 (2), 173-179, 2018 | 19 | 2018 |
| Performance investigation of GaSb/Si heterojunction based gate underlap and overlap vertical TFET biosensor A Theja, M Panchore IEEE Transactions on NanoBioscience 22 (2), 284-291, 2022 | 16 | 2022 |
| Dopingless-TFET leaky-integrated-fire (LIF) neuron for high-speed energy efficient applications S Singh, M Panchore IEEE transactions on nanotechnology 21, 110-117, 2022 | 16 | 2022 |
| Compact behavioral modeling and time dependent performance degradation analysis of junction and doping free transistors M Panchore, J Singh, SP Mohanty, E Kougianos 2016 IEEE international symposium on Nanoelectronic and information systems …, 2016 | 11 | 2016 |
| Low Power and High Speed CMOS Comparator Design Using 0.18 µm Technology RS Gamad, M Panchore International Journal of Electronic Engineering Research 2 (1), 71-77, 2010 | 10 | 2010 |
| Channel-hot-carrier degradation in the channel of junctionless transistors: a device-and circuit-level perspective M Panchore, L Bramhane, J Singh Journal of Computational Electronics 20 (3), 1196-1201, 2021 | 8 | 2021 |
| Impact of work function engineering in charge plasma based bipolar devices L Bramhane, S Salankar, M Gaikwad, M Panchore Silicon, 1-5, 2022 | 7 | 2022 |
| Realization of Boolean functions using heterojunction tunnel FETs V Ambekar, M Panchore Silicon 14 (11), 6467-6475, 2022 | 5 | 2022 |
| Impact of back gate bias on analog performance of dopingless transistor R Kumar, M Panchore Transactions on Electrical and Electronic Materials 24 (1), 115-121, 2023 | 4 | 2023 |
| Aging Mechanism of p-type dopingless JLFET: NBTI and channel-hot-carrier stress M Panchore, C Rajan Transactions on Electrical and Electronic Materials 24 (2), 154-158, 2023 | 3 | 2023 |
| Realization of high-speed logic functions using heterojunction vertical TFET V Ambekar, M Panchore Applied Physics A 129 (3), 166, 2023 | 3 | 2023 |
| Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells M Panchore, K Cecil, J Singh Silicon 13, 4527-4533, 2021 | 3 | 2021 |
| Design of a CMOS Comparator for A/D Converter Application M Panchore, RS Gamad, BC Nagar International Journal of Computational Intelligence and Information Security …, 2010 | 2 | 2010 |
| Performance assessment of charge plasma based hetero‐structure VTFET biosensor for linearity enhancement A Theja, M Panchore International Journal of Numerical Modelling: Electronic Networks, Devices …, 2024 | 1 | 2024 |
| A paradigm shift in analog applications through reconfigurable FET C Rajan, R Ghare, S Bhujade, M Panchore, B Neole Microelectronics Journal 142, 106004, 2023 | 1 | 2023 |
| Comparative Performance and Reliability Analysis of Doping and Junction Free Devices with High-κ/Vacuum Gate Dielectric R Kumar, M Panchore, L Bramhane, J Singh Silicon 14 (9), 5035-5039, 2022 | 1 | 2022 |
| High speed ultra-low-lower lulse-triggered JLFET Flip-Flop S Kumar, M Panchore, S Singh, J Singh Modern Physics Letters B 38 (10), 2450068, 2024 | | 2024 |
