Charlotte Frenkel
Charlotte Frenkel
Adresse e-mail validée de uclouvain.be
TitreCitée parAnnée
SleepTalker: A ULV 802.15. 4a IR-UWB transmitter SoC in 28-nm FDSOI achieving 14 pJ/b at 27 Mb/s with channel selection based on adaptive FBB and digitally programmable pulse …
G de Streel, F Stas, T Gurné, F Durant, C Frenkel, A Cathelin, D Bol
IEEE Journal of Solid-State Circuits 52 (4), 1163-1177, 2017
152017
A 0.086-mm 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS
C Frenkel, M Lefebvre, JD Legat, D Bol
IEEE Transactions on Biomedical Circuits and Systems 13 (1), 145-158, 2019
132019
A fully-synthesized 20-gate digital spike-based synapse with embedded online learning
C Frenkel, G Indiveri, JD Legat, D Bol
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
42017
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications
C Frenkel, JD Legat, D Bol
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
32016
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications
C Frenkel, JD Legat, D Bol
2015 10th International Symposium on Reconfigurable Communication-centric …, 2015
32015
A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors
C Frenkel, JD Legat, D Bol
2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2017
22017
SleepTalker: A 28nm FDSOI ULV 802.15. 4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape
G de Streel, F Stas, T Gurné, F Durant, C Frenkel, D Bol
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016
22016
A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning
C Frenkel, JD Legat, D Bol
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
12019
MorphIC: A 65-nm 738k-Synapse/mm Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning
C Frenkel, JD Legat, D Bol
arXiv preprint arXiv:1904.08513, 2019
2019
19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode
D Bol, M Schramme, L Moreau, T Haine, P Xu, C Frenkel, R Dekimpe, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 322-324, 2019
2019
A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode
D Bol, M Schramme, L Moreau, T Haine, P Xu, C Frenkel, R Dekimpe, ...
2019
Neuromorphic CMOS imager for sparse vision data acquisition
N ROUSSEAU, D BOL, D FLANDRE, C FRENKEL, JD LEGAT
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