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Giovanni Brignone
Giovanni Brignone
PhD student, Politecnico di Torino
Adresse e-mail validée de polito.it
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To spike or not to spike: A digital hardware perspective on deep learning acceleration
F Ottati, C Gao, Q Chen, G Brignone, MR Casu, JK Eshraghian, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2023
82023
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs
G Brignone, MU Jamal, MT Lazarescu, L Lavagno
IEEE Access 10, 118858-118877, 2022
22022
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
G Brignone, MT Lazarescu, L Lavagno
2023 IEEE 41st International Conference on Computer Design (ICCD), 551-557, 2023
2023
Acceleration by Separate-Process Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis
G Brignone
Politecnico di Torino, 2021
2021
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