| Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias Y Badr, A Torres, P Gupta Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 62 | 2015 |
| Incorporating DSA in multipatterning semiconductor manufacturing technologies Y Badr, JA Torres, Y Ma, J Mitra, P Gupta Design-Process-Technology Co-optimization for Manufacturability IX 9427, 182-189, 2015 | 30 | 2015 |
| Layout pattern-driven design rule evaluation Y Badr, K Ma, P Gupta Journal of Micro/Nanolithography, MEMS, and MOEMS 13 (4), 043018-043018, 2014 | 17 | 2014 |
| Comprehensive die-level assessment of design rules and layouts RS Ghaida, Y Badr, M Gupta, N Jin, P Gupta 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 61-66, 2014 | 13 | 2014 |
| Assessing benefits of a buried interconnect layer in digital designs L Zhu, Y Badr, S Wang, S Iyer, P Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 11 | 2016 |
| Mask assignment and DSA grouping for DSA-MP hybrid lithography for sub-7 nm contact/via holes Y Badr, A Torres, P Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 6 | 2016 |
| Dynamic programming approach to adaptive slicing for optimization under a global volumetric error constraint A Deng, Y Badr, P Gupta Laser 3D manufacturing V 10523, 41-51, 2018 | 5 | 2018 |
| A hashing mechanism for rule-based decomposition in Double Patterning Photolithography HA Darwish, HN Shagar, YA Badr, YH Arafa, AG Wassal 2010 International Conference on Microelectronics, 363-366, 2010 | 5 | 2010 |
| Technology path-finding framework for directed-self assembly for via layers Y Badr, P Gupta Journal of Micro/Nanolithography, MEMS, and MOEMS 16 (1), 013505-013505, 2017 | 3 | 2017 |
| Selected Papers on Directed Self Assembly (DSA) Y Badr SPIE, UCLA, NanoCAD Lab, 2014 | 3 | 2014 |
| Split-it!: from litho etch litho etch to self-aligned double patterning decomposition YA Badr, AG Wassal, S Hammouda Photomask Technology 2012 8522, 624-631, 2012 | 3 | 2012 |
| Pattern-restricted design at 10nm and beyond RS Ghaida, Y Badr, P Gupta 2014 IEEE 32nd International Conference on Computer Design (ICCD), 308-310, 2014 | 2 | 2014 |
| Co-optimization of Restrictive Patterning Technologies and Design YAZ Badr University of California, Los Angeles, 2017 | 1 | 2017 |
| Hotspot-aware DSA Grouping and Mask Assignment Y Badr, P Gupta arXiv preprint arXiv:1710.02921, 2017 | | 2017 |
| Technology path-finding for directed self-assembly for via layers Y Badr, P Gupta Design-Process-Technology Co-optimization for Manufacturability XI 10148, 95-108, 2017 | | 2017 |
| Analog, Mixed-Signal, and RF Circuits C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance … Y Badr, A Torres, P Gupta | | |
| Map Reduce Y Badr | | |
| Self Aligned Quadruple Patterning Y Badr | | |
| Selected Papers on Directed Self Assembly (DSA) SPIE’14 Y Badr | | |
PUNEET GUPTAUCLA Electrical and Computer EngineeringAdresse e-mail validée de g.ucla.edu
