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Nodari Sitchinava
Nodari Sitchinava
Adresse e-mail validée de hawaii.edu - Page d'accueil
Titre
Citée par
Citée par
Année
Sorting, searching, and simulation in the mapreduce framework
MT Goodrich, N Sitchinava, Q Zhang
International Symposium on Algorithms and Computation, 374-383, 2011
2872011
Fundamental parallel algorithms for private-cache chip multiprocessors
L Arge, MT Goodrich, M Nelson, N Sitchinava
Proceedings of the twentieth annual symposium on Parallelism in algorithms …, 2008
1582008
A reconfigurable shared scan-in architecture
S Samaranayake, E Gizdarski, N Sitchinava, F Neuveux, R Kapur, ...
Proceedings. 21st VLSI Test Symposium, 2003., 9-14, 2003
1182003
Changing the scan enable during shift
N Sitchinava, E Gizdarski, S Samaranayake, F Neuveux, R Kapur, ...
22nd IEEE VLSI Test Symposium, 2004. Proceedings., 73-78, 2004
902004
Parallel external memory graph algorithms
L Arge, MT Goodrich, N Sitchinava
2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010
472010
Guard placement for efficient point-in-polygon proofs
D Eppstein, MT Goodrich, N Sitchinava
Proceedings of the twenty-third annual symposium on Computational geometry …, 2007
40*2007
Dynamic scan: Driving down the cost of test
S Samaranayake, N Sitchinava, R Kapur, MB Amin, TW Williams
Computer 35 (10), 63-68, 2002
372002
Efficient parallel and external matching
M Birn, V Osipov, P Sanders, C Schulz, N Sitchinava
European Conference on Parallel Processing, 659-670, 2013
312013
Lower bounds in the asymmetric external memory model
R Jacob, N Sitchinava
Proceedings of the 29th ACM Symposium on Parallelism in Algorithms and …, 2017
272017
Dynamically reconfigurable shared scan-in test architecture
R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, F Neuveux, ...
US Patent 7,418,640, 2008
272008
Dynamically reconfigurable shared scan-in test architecture
R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, FJ Neuveux, ...
US Patent 7,900,105, 2011
202011
Geometric algorithms for private-cache chip multiprocessors
D Ajwani, N Sitchinava, N Zeh
Algorithms–ESA 2010: 18th Annual European Symposium, Liverpool, UK …, 2010
202010
Analysis-driven engineering of comparison-based sorting algorithms on GPUs
B Karsin, V Weichert, H Casanova, J Iacono, N Sitchinava
Proceedings of the 2018 International Conference on Supercomputing, 86-95, 2018
19*2018
A parallel buffer tree
N Sitchinava, N Zeh
Proceedings of the twenty-fourth annual ACM symposium on Parallelism in …, 2012
192012
Dynamically reconfigurable shared scan-in test architecture
R Kapur, N Sitchinava, S Samaranayake, E Gizdarski, FJ Neuveux, ...
US Patent 7,596,733, 2009
192009
Parallel algorithms in geometry
MT Goodrich, N Sitchinava
Handbook of Discrete and Computational Geometry, 1225-1239, 2017
182017
Provably efficient GPU algorithms
N Sitchinava, V Weichert
CoRR, abs/1306.5076, 2013
162013
On the complexity of list ranking in the parallel external memory model
R Jacob, T Lieber, N Sitchinava
Mathematical Foundations of Computer Science 2014: 39th International …, 2014
142014
On (dynamic) range minimum queries in external memory
L Arge, J Fischer, P Sanders, N Sitchinava
Workshop on Algorithms and Data Structures, 37-48, 2013
132013
Beyond binary search: parallel in-place construction of implicit search tree layouts
K Berney, H Casanova, B Karsin, N Sitchinava
IEEE Transactions on Computers 71 (5), 1104-1116, 2021
122021
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