| Analysis and design of cost-effective, high-throughput LDPC decoders TT Nguyen-Ly, V Savin, K Le, D Declercq, F Ghaffari, O Boncalo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 508-521, 2017 | 47 | 2017 |
| FPGA design of high throughput LDPC decoder based on imprecise offset min-sum decoding T Nguyen-Ly, K Le, F Ghaffari, A Amaricai, O Boncalo, V Savin, ... 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015 | 37 | 2015 |
| Efficient hardware implementation of probabilistic gradient descent bit-flipping K Le, F Ghaffari, D Declercq, B Vasić IEEE Transactions on Circuits and Systems I: Regular Papers 64 (4), 906-917, 2016 | 32 | 2016 |
| Non-surjective finite alphabet iterative decoders TT Nguyen-Ly, K Le, V Savin, D Declercq, F Ghaffari, O Boncalo 2016 IEEE International Conference on Communications (ICC), 1-6, 2016 | 25 | 2016 |
| Approaching maximum likelihood performance of LDPC codes by stochastic resonance in noisy iterative decoders B Vasić, P Ivaniš, D Declercq, K LeTrung 2016 Information Theory and Applications Workshop (ITA), 1-9, 2016 | 24 | 2016 |
| An adaptation of min-sum decoder for 5G low-density parity-check codes K Le Trung, F Ghaffari, D Declercq 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 20 | 2019 |
| Efficient realization of probabilistic gradient descent bit flipping decoders K Le, D Declercq, F Ghaffari, C Spagnol, E Popovici, P Ivanis, B Vasic 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1494-1497, 2015 | 20 | 2015 |
| Variable-node-shift based architecture for probabilistic gradient descent bit flipping on QC-LDPC codes K Le, D Declercq, F Ghaffari, L Kessal, O Boncalo, V Savin IEEE Transactions on Circuits and Systems I: Regular Papers 65 (7), 2183-2195, 2017 | 18 | 2017 |
| A probabilistic parallel bit-flipping decoder for low-density parity-check codes K Le, F Ghaffari, L Kessal, D Declercq, E Boutillon, C Winstead, B Vasić IEEE Transactions on Circuits and Systems I: Regular Papers 66 (1), 403-416, 2018 | 15 | 2018 |
| A novel high-throughput, low-complexity bit-flipping decoder for LDPC codes K Le, F Ghaffari, D Declercq, B Vasic, C Winstead 2017 International Conference on Advanced Technologies for Communications …, 2017 | 12 | 2017 |
| Efficient FPGA implementation of probabilistic gallager B LDPC decoder F Ghaffari, B Unal, A Akoglu, K Le, D Declercq, B Vasić 2017 24th IEEE International Conference on Electronics, Circuits and Systems …, 2017 | 7 | 2017 |
| On the use of hard-decision ldpc decoders on mlc nand flash memory K Le, F Ghaffari 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD …, 2018 | 6 | 2018 |
| Power gating technique in pacemaker design on FPGA H Trang The 2012 International Conference on Advanced Technologies for …, 2012 | 6 | 2012 |
| Design an optimized CPU architecture for pacemaker applications LT Khoa, H Trang 4th International Conference on Biomedical Engineering in Vietnam, 50-53, 2013 | 5 | 2013 |
| Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding DP Nguyen, K Le, F Ghaffari, D Declercq 2019 19th International Symposium on Communications and Information …, 2019 | 3 | 2019 |
| The probabilistic finite alphabet iterative decoder for low-density parity-check codes F Ghaffari, K Le, D Declercq 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2019 | 3 | 2019 |
| An enhanced offset min-sum decoder for 5G LDPC codes H Cui, K Le Trung, F Ghaffari, D Declercq, J Lin, Z Wang 2019 25th Asia-Pacific Conference on Communications (APCC), 490-495, 2019 | 2 | 2019 |
| On the use of probabilistic parallel bit-flipping decoder for the storage systems K Le, F Ghaffari, D Declercq 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 2 | 2018 |
| New direction on low complexity implementation of probabilistic gradient descent bit-flipping decoder K Le Trung université de cergy-pontoise, 2017 | 2 | 2017 |
| Lightweight hardware architecture for probabilistic gradient descent bit flipping on QC-LDPC codes K Le, F Ghaffari, L Kessal, D Declercq, V Savin, O Boncalo 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 1 | 2018 |
Declercq DavidProfesseur des Universités, ENSEAVerified email at ensea.fr
