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Jacek Bieganowski
Jacek Bieganowski
Verified email at imei.uz.zgora.pl
Title
Cited by
Cited by
Year
Detection of deadlocks and traps in Petri nets by means of Thelen's prime implicant method
A Węgrzyn, A Karatkevich, J Bieganowski
International Journal of Applied Mathematics and Computer Science 14 (1 …, 2004
412004
Logic synthesis for finite state Machines Based on Linear Chains of States
A Barkalov, L Titarenko, J Bieganowski
Studies in Systems, Decision and Control, Springer, Berlin, 2018
112018
Synthesis of microprogram control units oriented toward decreasing the number of macrocells of addressing circuit
J Bieganowski
University of Zielona Góra Press, 2011
112011
Heuristics for Thelen’s prime implicant method
J Bieganowski, A Karatkevich
Schedae Informaticae 14, 125, 2005
82005
Reduction in the number of LUT elements for control units with code sharing
A Barkalov, L Titarenko, J Bieganowski
International Journal of Applied Mathematics and Computer Science 20 (4 …, 2010
72010
Design of FPGA-based Moore FMSs with counters
A Barkalov, L Titarenko, J Bieganowski
IFAC Proceedings Volumes 46 (28), 171-174, 2013
62013
Synthesis of control unit with modified operational linear chains
AA Barkalov, L Titarenko, J Bieganowski
Pomiary Automatyka Kontrola 53 (5), 15-17, 2007
62007
Optimization of compositional microprogram control unit by modification of microinstruction format
L Titarenko, J Bieganowski
Electronics and Telecommunications Quarterly 55 (2), 201-214, 2009
42009
Synthesis of control unit with modified microinstructions
A Barkalov, L Titarenko, J Bieganowski
2007 14th International Conference on Mixed Design of Integrated Circuits …, 2007
42007
Microprogram control unit with code sharing and extended microinstruction format
A Barkalov, L Titarenko, J Bieganowski
2010 East-West Design & Test Symposium (EWDTS), 73-76, 2010
32010
„Język Verilog w projektowaniu układów FPGA
J Bieganowski, G Wawrzyniak
Zielona Góra, 2001
32001
Designing HFPGA-based FSMs with counters
A Barkalov, L Titarenko, J Bieganowski
2017 MIXDES-24th International Conference" Mixed Design of Integrated …, 2017
22017
Code sharing in FPGA-based Moore FSMs
J Bieganowski, A Barkalov, L Titarenko, W Zajac
International Conference of Computational Methods in Sciences and …, 2015
22015
8 Synthesis of Compositional Microprogram Control Unit with Dedicated Area of Inputs
A Barkalov, L Titarenko, J Bieganowski, A Miroshkin
Design of Digital Systems and Devices, 193-214, 2011
22011
Synthesis of compositional microprogram control unit with extended microinstruction format
A Barkalov, L Titarenko, J Bieganowski
2009 MIXDES-16th International Conference Mixed Design of Integrated …, 2009
22009
Synthesis of microprogram control unit with control microinstructions
A Barkalov, L Titarenko, J Bieganowski
IFAC Proceedings Volumes 42 (21), 201-204, 2009
22009
Finite state machines and field-programmable gate arrays
A Barkalov, L Titarenko, J Bieganowski, A Barkalov, L Titarenko, ...
Logic Synthesis for Finite State Machines Based on Linear Chains of States …, 2018
12018
Design of control unit with modified operational linear chains
AA Barkalov, L Titarenko, J Bieganowski
2008 International Conference on" Modern Problems of Radio Engineering …, 2008
12008
Heurystyki dla metody Thelena obliczania implikantów prostych
J Bieganowski, A Karatkevich
Materiały IV Krajowej konferencji Metody i systemy komputerowe w badaniach …, 0
1
Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review
A Barkalov, L Titarenko, J Bieganowski, K Krzywicki
Applied Sciences 14 (7), 2693, 2024
2024
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