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IPP@ HDL: efficient intellectual property protection scheme for IP cores
E Castillo, U Meyer-Baese, A García, L Parrilla, A Lloris
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (5), 578-591, 2007
Ring oscillators as thermal sensors in FPGAs: Experiments in low voltage
JJL Franco, E Boemo, E Castillo, L Parrilla
2010 VI Southern Programmable Logic Conference (SPL), 133-137, 2010
Efficient wavelet-based ECG processing for single-lead FHR extraction
E Castillo, DP Morales, G Botella, A García, L Parrilla, AJ Palma
Digital Signal Processing 23 (6), 1897-1909, 2013
Noise suppression in ECG signals through efficient one-step wavelet processing techniques
E Castillo, DP Morales, A García, F Martínez-Martí, L Parrilla, AJ Palma
Journal of Applied Mathematics 2013, 2013
RNS-FPL merged architectures for orthogonal DWT
J Ramírez, A García, PG Fernández, L Parrilla, A Lloris
Electronics Letters 36 (14), 1198-1199, 2000
A new architecture to compute the discrete cosine transform using the quadratic residue number system
J Ramírez, A Garcia, PG Fernández, L Parrilla, A Lloris
2000 IEEE International Symposium on Circuits and Systems (ISCAS) 5, 321-324, 2000
An application of reconfigurable technologies for non-invasive fetal heart rate extraction
DP Morales, A Garcia, E Castillo, MA Carvajal, L Parrilla, AJ Palma
Medical Engineering & Physics 35 (7), 1005-1014, 2013
A RNS-based matrix-vector-multiply FCT architecture for DCT computation
PG Fernandez, A Garcia, J Ramirez, L Parrilla, A Lloris
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat …, 2000
Minimum-clock-cycle Itoh-Tsujii algorithm hardware implementation for cryptography applications over GF (2m) fields
L Parrilla, A Lloris, E Castillo, A Garcia
Electronics letters 48 (18), 1126-1128, 2012
Automated signature insertion in combinational logic patterns for HDL IP core protection
E Castillo, L Parrilla, A Garcia, U Meyer-Baese, G Botella, A Lloris
2008 4th Southern Conference on Programmable Logic, 183-186, 2008
IPP watermarking technique for IP core protection on FPL devices
E Castillo, L Parrilla, A Garcia, A Loris, U Meyer-Baese
2006 International Conference on Field Programmable Logic and Applications, 1-6, 2006
Intellectual property protection (IPP) using obfuscation in C, VHDL, and verilog coding
U Meyer-Bäse, E Castillo, G Botella, L Parrilla, A Garcia
Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and …, 2011
Sistemas digitales
A Lloris Ruíz, A Prieto Espinosa, L Parrilla Roure
A new implementation of the discrete cosine transform in the residue number system
PG Fernández, A García, J Ramírez, L Parrilla, A Lloris
Conference Record of the Thirty-Third Asilomar Conference on Signals …, 1999
Nondeterministic AND-EXOR minimisation by using rewrite rules and simulated annealing
L Parrilla, J Ortega, A Lloris
IEE Proceedings-Computers and Digital Techniques 146 (1), 1-8, 1999
Analysis of RNS-FPL synergy for high throughput DSP applications: Discrete wavelet transform
J Ramírez, A García, PG Fernández, L Parrilla, A Lloris
International Workshop on Field Programmable Logic and Applications, 342-351, 2000
Unified compact ECC-AES co-processor with group-key support for IoT devices in wireless sensor networks
L Parrilla, E Castillo, JA López-Ramos, JA Álvarez-Bermejo, A García, ...
Sensors 18 (1), 251, 2018
Hardware activation by means of PUFs and elliptic curve cryptography in field-programmable devices
L Parrilla, E Castillo, DP Morales, A García
Electronics 5 (1), 5, 2016
Towards project-based learning applied to the electronic engineering studies
DP Morales, E Castillo, L Parrilla, A García, A Otín
2015 Conference on Design of Circuits and Integrated Systems (DCIS), 1-5, 2015
Elliptic Curve Cryptography hardware accelerator for high-performance secure servers
L Parrilla, JA Álvarez-Bermejo, E Castillo, JA López-Ramos, ...
The Journal of Supercomputing 75 (3), 1107-1122, 2019
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