| Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET Y Choi, K Lee, KY Kim, S Kim, J Lee, R Lee, HM Kim, YS Song, S Kim, ... Solid-State Electronics 164, 107686, 2020 | 49 | 2020 |
| Wakeup-free and endurance-robust ferroelectric field-effect transistor memory using high pressure annealing MC Nguyen, S Kim, K Lee, JY Yim, R Choi, D Kwon IEEE Electron Device Letters 42 (9), 1295-1298, 2021 | 44 | 2021 |
| Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs S Kim, M Kim, D Ryu, K Lee, S Kim, J Lee, R Lee, S Kim, JH Lee, BG Park IEEE Transactions on Electron Devices 67 (6), 2648-2652, 2020 | 38 | 2020 |
| Effects of high-pressure annealing on the low-frequency noise characteristics in ferroelectric FET W Shin, JH Bae, S Kim, K Lee, D Kwon, BG Park, D Kwon, JH Lee IEEE Electron Device Letters 43 (1), 13-16, 2021 | 35 | 2021 |
| Ferroelectric-gate field-effect transistor memory with recessed channel K Lee, JH Bae, S Kim, JH Lee, BG Park, D Kwon IEEE Electron Device Letters 41 (8), 1201-1204, 2020 | 27 | 2020 |
| Incremental drain-voltage-ramping training method for ferroelectric field-effect transistor synaptic devices MC Nguyen, K Lee, S Kim, S Youn, Y Hwang, H Kim, R Choi, D Kwon IEEE Electron Device Letters 43 (1), 17-20, 2021 | 19 | 2021 |
| Effects of process-induced defects on polarization switching in ferroelectric tunneling junction memory K Lee, S Kim, JH Lee, BG Park, D Kwon IEEE Electron Device Letters 42 (3), 323-326, 2021 | 18 | 2021 |
| Investigation of device performance for fin angle optimization in FinFET and gate-all-around FETs for 3 nm-node and beyond S Kim, K Lee, S Kim, M Kim, JH Lee, S Kim, BG Park IEEE Transactions on Electron Devices 69 (4), 2088-2093, 2022 | 17 | 2022 |
| Vertically stacked gate-all-around structured tunneling-based ternary-CMOS S Kim, K Lee, JH Lee, D Kwon, BG Park IEEE Transactions on Electron Devices 67 (9), 3889-3893, 2020 | 17 | 2020 |
| Surface Ge-rich p-type SiGe channel tunnel field-effect transistor fabricated by local condensation technique J Lee, R Lee, S Kim, K Lee, HM Kim, S Kim, M Kim, S Kim, JH Lee, ... Solid-State Electronics 164, 107701, 2020 | 16 | 2020 |
| Demonstration of tunneling field-effect transistor ternary inverter HW Kim, S Kim, K Lee, J Lee, BG Park, D Kwon IEEE Transactions on Electron Devices 67 (10), 4541-4544, 2020 | 15 | 2020 |
| Analysis on reverse drain-induced barrier lowering and negative differential resistance of ferroelectric-gate field-effect transistor memory K Lee, S Kim, JH Lee, D Kwon, BG Park IEEE Electron Device Letters 41 (8), 1197-1200, 2020 | 13 | 2020 |
| Negative capacitance effect on MOS structure: Influence of electric field variation K Lee, J Lee, S Kim, R Lee, S Kim, M Kim, JH Lee, S Kim, BG Park IEEE Transactions on Nanotechnology 19, 168-171, 2020 | 12 | 2020 |
| Double-gated ferroelectric-gate field-effect-transistor for processing in memory M Kim, K Lee, S Kim, JH Lee, BG Park, D Kwon IEEE Electron Device Letters 42 (11), 1607-1610, 2021 | 11 | 2021 |
| Comprehensive TCAD-based validation of interface trap-assisted ferroelectric polarization in ferroelectric-gate field-effect transistor memory K Lee, S Kim, M Kim, JH Lee, D Kwon, BG Park IEEE Transactions on Electron Devices 69 (3), 1048-1053, 2022 | 10 | 2022 |
| Physical unclonable functions using ferroelectric tunnel junctions S Kim, K Lee, MH Oh, JH Lee, BG Park, D Kwon IEEE Electron Device Letters 42 (6), 816-819, 2021 | 10 | 2021 |
| Investigation on ambipolar current suppression using a stacked gate in an L-shaped tunnel field-effect transistor J Yu, S Kim, D Ryu, K Lee, C Kim, JH Lee, S Kim, BG Park Micromachines 10 (11), 753, 2019 | 10 | 2019 |
| Suppression of reverse drain induced barrier lowering in negative capacitance FDSOI field effect transistor using oxide charge trapping layer K Lee, S Kim, JH Lee, D Kwon, BG Park Semiconductor Science and Technology 35 (12), 125003, 2020 | 6 | 2020 |
| Ferroelectric-metal field-effect transistor with recessed channel for 1T-DRAM application K Lee, S Kim, JH Lee, BG Park, D Kwon IEEE Journal of the Electron Devices Society 10, 13-18, 2021 | 5 | 2021 |
| Gate-first negative capacitance field-effect transistor with self-aligned nickel-silicide source and drain S Kim, K Lee, JH Lee, BG Park, D Kwon IEEE Transactions on Electron Devices 68 (9), 4754-4757, 2021 | 5 | 2021 |
Byung Gook ParkProfessor of Electrical Engineering, Seoul National UniversityAdresse e-mail validée de snu.ac.kr
