Madhu Mutyam

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Vijaykrishnan NarayananRobert Noll Chair Professor at The Pennsylvania State UniversityAdresse e-mail validée de cse.psu.edu
John JoseAssociate Professor, Department of Computer Science & Engineering, IIT GuwahatiAdresse e-mail validée de iitg.ac.in
Mary Jane (Janie) IrwinEmerita Evan Pugh University Professor, CSE, Penn State UniversityAdresse e-mail validée de cse.psu.edu
Kamakoti VeezhinathanProfessor, Department of Computer Science, IIT MadrasAdresse e-mail validée de cse.iitm.ac.in
Debiprasanna SahooIndian Institute of Technology RoorkeeAdresse e-mail validée de cs.iitr.ac.in
Mahmut KandemirPennsylvania State UniversityAdresse e-mail validée de psu.edu
Yuan XieProfessor of University of California at Santa BarbaraAdresse e-mail validée de ece.ucsb.edu
Biswabandan PandaIIT BombayAdresse e-mail validée de iitb.ac.in
Rodica CeterchiProfessor of Computer Science, University of Bucharest, Faculty of Mathematics and CSAdresse e-mail validée de fmi.unibuc.ro
Arpit JoshiIntelAdresse e-mail validée de intel.com
Gnaneswara Rao JonnaDoctoral Research Scholar at IIT MADRASAdresse e-mail validée de cse.iitm.ac.in
A. Vinaya BabuStanley College of Engineering & Technology for WomenAdresse e-mail validée de jntuh.ac.in
Praveen AlapatiIndian Institute of Technology MadrasAdresse e-mail validée de cse.iitm.ac.in
Partha RoopProfessor, Electrical, Computer and Software Engineering, The University of AucklandAdresse e-mail validée de auckland.ac.nz
Ramesh S.formerly Professor of Computer Science, IIT Bombay, now Technical Fellow, General Motors R&DAdresse e-mail validée de iitbombay.org
Sakthi BalanAssociate ProfessorAdresse e-mail validée de lnmiit.ac.in
Prasanna RengasamyGoogleAdresse e-mail validée de psu.edu
Pritam MajumderPhD student in Texas A&M UniversityAdresse e-mail validée de neo.tamu.edu
K.G. SubramanianProfessor

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Madhu Mutyam

Professor, Department of CSE, Indian Institute of Technology Madras

Adresse e-mail validée de cse.iitm.ac.in - Page d'accueil

Computer Architecture Memory Technologies Networks on Chip Multicore Architecture VLSI CAD


Titre Trier par citations Trier par année Trier par titre	Citée par Citée par	Année
Array-rewriting P systems R Ceterchi, M Mutyam, G Păun, KG Subramanian Natural Computing 2, 229-249, 2003	106	2003
P systems with membrane creation: Universality and efficiency M Mutyam, K Krithivasan Machines, Computations, and Universality: Third International Conference …, 2001	67	2001
A bus encoding technique for power and cross-talk minimization P Subrahmanya, R Manimegalai, V Kamakoti, M Mutyam 17th International Conference on VLSI Design. Proceedings., 443-448, 2004	57	2004
Dynamic coding technique for low-power data bus M Madhu, VS Murty, V Kamakoti IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 252-253, 2003	46	2003
DeBAR: Deflection based adaptive router with minimal buffering J Jose, B Nayak, K Kumar, M Mutyam 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013	45	2013
Compiler-directed thermal management for VLIW functional units M Mutyam, F Li, V Narayanan, M Kandemir, MJ Irwin Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers …, 2006	45	2006
Preventing crosstalk delay using Fibonacci representation M Mutyam 17th International Conference on VLSI Design. Proceedings., 685-688, 2004	44	2004
Working with process variation aware caches M Mutyam, V Narayanan 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007	40	2007
Process-variation-aware adaptive cache architecture and management M Mutyam, F Wang, R Krishnan, V Narayanan, M Kandemir, Y Xie, ... IEEE Transactions on Computers 58 (7), 865-877, 2009	29	2009
Probabilistic rewriting P systems M Madhu International Journal of Foundations of Computer Science 14 (01), 157-166, 2003	23	2003
Fibonacci codes for crosstalk avoidance M Mutyam IEEE Transactions on very large scale integration (vlsi) systems 20 (10 …, 2011	22	2011
Selective shielding: a crosstalk-free bus encoding technique M Mutyam 2007 IEEE/ACM International Conference on Computer-Aided Design, 618-621, 2007	21	2007
Contextual P systems K Krithivasan, M Madhu Fundamenta Informaticae 49 (1-3), 179-189, 2002	21	2002
An application-aware cache replacement policy for last-level caches TS Warrier, B Anupama, M Mutyam Architecture of Computing Systems–ARCS 2013: 26th International Conference …, 2013	18	2013
Minimally buffered single-cycle deflection router GR Jonna, J Jose, R Radhakrishnan, M Mutyam 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014	17	2014
On a class of P automata M Madhu, K Krithivasan International journal of computer mathematics 80 (9), 1111-1120, 2003	17	2003
Improved results about universality of P systems M Madhu, K Krithivasan Bulletin of the EATCS 76, 162-168, 2002	17	2002
Variation analysis of CAM cells A Mupid, M Mutyam, N Vijaykrishnan, Y Xie, MJ Irwin 8th International Symposium on Quality Electronic Design (ISQED'07), 333-338, 2007	16	2007
Block remap with turnoff: a variation-tolerant cache design technique MA Hussain, M Mutyam 2008 Asia and South Pacific Design Automation Conference, 783-788, 2008	14	2008
Delay and energy efficient data transmission for on-chip buses M Mutyam, M Eze, N Vijaykrishnan, Y Xie IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006	14	2006

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