Serge Bernard
Serge Bernard
LIRMM, CNRS/Université de montpellier
Adresse e-mail validée de lirmm.fr
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Towards an ADC BIST scheme using the histogram test technique
F Azais, S Bernard, Y Betrand, M Renovell
Proceedings IEEE European Test Workshop, 53-58, 2000
1092000
Implementation of a linear histogram BIST for ADCs
F Azaïs, S Bernard, Y Bertrand, M Renovell
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
1032001
Hardware resource minimization for histogram-based ADC BIST
M Renovell, F Azaïs, S Bernard, Y Bertrand
Proceedings 18th IEEE VLSI Test Symposium, 247-252, 2000
912000
A low-cost adaptive ramp generator for analog BIST applications
F Azaïs, S Bernard, Y Bertrand, X Michel, M Renovell
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 266-271, 2001
902001
A high accuracy triangle-wave signal generator for on-chip ADC testing
S Bernard, F Azaïs, Y Bertrand, M Renovell
Proceedings The Seventh IEEE European Test Workshop, 89-94, 2002
792002
A low-cost BIST architecture for linear histogram testing of ADCs
F Azaïs, S Bernard, Y Bertrand, M Renovell
Journal of Electronic Testing 17 (2), 139-147, 2001
432001
DC-100-GHz frequency doublers in InP DHBT technology
V Puyal, A Konczykowska, P Nouet, S Bernard, S Blayac, F Jorge, M Riet, ...
IEEE Transactions on Microwave theory and techniques 53 (4), 1338-1344, 2005
372005
Making predictive analog/RF alternate test strategy independent of training set size
H Ayari, F Azais, S Bernard, M Comte, V Kerzerho, O Potin, M Renovell
2012 IEEE International Test Conference, 1-9, 2012
362012
Smart selection of indirect parameters for DC-based alternate RF IC testing
H Ayari, F Azais, S Bernard, M Comte, M Renovell, V Kerzerho, O Potin, ...
2012 IEEE 30th VLSI Test Symposium (VTS), 19-24, 2012
342012
Device for distributing power between cathodes of a multipolar electrode, in particular of an implant
D Andreu, S Bernard, Y Bertrand, G Catheras, J Galy, D Guiraud, ...
US Patent 7,768,151, 2010
332010
New implantable stimulator for the FES of paralyzed muscles
JD Techer, S Bernard, Y Bertrand, G Cathébras, D Guiraud
Proceedings of the 30th European Solid-State Circuits Conference, 455-458, 2004
242004
Efficient on-chip generator for linear histogram BIST of ADCs
S Bernard, F Azais, Y Bertrand, M Renovell
Proc. International Mixed-Signal Testing Workshop, 89-96, 2001
202001
A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs
V Kerzerho, P Cauvet, S Bernard, F Azais, M Comte, M Renovell
IEEE Design & Test of Computers 23 (3), 234-243, 2006
192006
Optimizing sinusoidal histogram test for low cost ADC BIST
F Azaïs, S Bernard, Y Bertrand, M Renovell
Journal of Electronic Testing 17 (3-4), 255-266, 2001
192001
Fast digital post-processing technique for integral nonlinearity correction of analog-to-digital converters: Validation on a 12-bit folding-and-interpolating analog-to-digital …
V Kerzérho, V Fresnaud, D Dallet, S Bernard, L Bossuet
IEEE Transactions on Instrumentation and Measurement 60 (3), 768-775, 2010
172010
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies
S Larguech, F Azaïs, S Bernard, M Comte, V Kerzérho, M Renovell
Microelectronics Journal 46 (11), 1091-1102, 2015
162015
A broad-band active frequency doubler operating up to 120 GHz
V Puyal, A Konczykowska, P Nouet, S Bernard, M Riet, F Jorge, J Godin
European Gallium Arsenide and Other Semiconductor Application Symposium …, 2005
162005
On-chip generation of ramp and triangle-wave stimuli for ADC BIST
S Bernard, F Azaïs, Y Bertrand, M Renovell
Journal of Electronic Testing 19 (4), 469-479, 2003
162003
Analog BIST generator for ADC testing
S Bernard, F Azaïs, Y Bertrand, M Renovell
Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance …, 2001
162001
Securing color information of an image by concealing the color palette
M Chaumont, W Puech, C Lahanier
Journal of Systems and Software 86 (3), 809-825, 2013
152013
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