Vikramkumar Pudi
Vikramkumar Pudi
IIT Tirupati
Adresse e-mail validée de iittp.ac.in
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Low complexity design of ripple carry and Brent–Kung adders in QCA
V Pudi, K Sridharan
IEEE Transactions on nanotechnology 11 (1), 105-119, 2011
1702011
Efficient design of a hybrid adder in quantum-dot cellular automata
V Pudi, K Sridharan
IEEE transactions on very large scale integration (VLSI) systems 19 (9 …, 2010
1162010
New decomposition theorems on majority logic for low-delay adder designs in quantum dot cellular automata
V Pudi, K Sridharan
IEEE Transactions on Circuits and Systems II: Express Briefs 59 (10), 678-682, 2012
732012
Efficient multiternary digit adder design in CNTFET technology
K Sridharan, S Gurindagunta, V Pudi
IEEE transactions on Nanotechnology 12 (3), 283-287, 2013
412013
A bit-serial pipelined architecture for high-performance DHT computation in quantum-dot cellular automata
V Pudi, K Sridharan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (10 …, 2014
302014
Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology
K Sridharan, V Pudi
Springer, 2015
232015
Secure and lightweight compressive sensing using stream cipher
V Pudi, A Chattopadhyay, KY Lam
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (3), 371-375, 2017
212017
Security vulnerabilities of unmanned aerial vehicles and countermeasures: An experimental study
V Dey, V Pudi, A Chattopadhyay, Y Elovici
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
202018
Efficient design of Baugh-Wooley multiplier in quantum-dot cellular automata
V Pudi, K Sridharan
2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013 …, 2013
142013
Cordic-based azimuth calculation and obstacle tracing via optimal sensor placement on a mobile robot
P Vyas, L Vachhani, K Sridharan, V Pudi
IEEE/ASME Transactions on Mechatronics 21 (5), 2317-2329, 2015
102015
CoLPUF: a novel configurable LFSR-based PUF
B Srinivasu, P Vikramkumar, A Chattopadhyay, KY Lam
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 358-361, 2018
72018
Efficient QCA design of single-bit and multi-bit subtractors
V Pudi, K Sridharan
2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013 …, 2013
72013
SHA-3 implementation using ReRAM based in-memory computing architecture
D Bhattacharjee, V Pudi, A Chattopadhyay
2017 18th International Symposium on Quality Electronic Design (ISQED), 325-330, 2017
62017
An FPGA-based brain computer interfacing using compressive sensing and machine learning
RR Shrivastwa, V Pudi, A Chattopadhyay
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 726-731, 2018
52018
Majority logic formulations for parallel adder designs at reduced delay and circuit complexity
V Pudi, K Sridharan, F Lombardi
IEEE transactions on computers 66 (10), 1824-1830, 2017
52017
Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle
T Nou-Shene, V Pudi, K Sridharan, V Thomas, J Arthi
IET Computer Vision 9 (4), 559-569, 2015
52015
Lightweight secure-boot architecture for risc-v system-on-chip
J Haj-Yahya, MM Wong, V Pudi, S Bhasin, A Chattopadhyay
20th International Symposium on Quality Electronic Design (ISQED), 216-223, 2019
32019
Efficient vlsi architectures for the hadamard transform based on offset-binary coding and rom decomposition
BS Kumar, V Pudi, K Sridharan
2011 IEEE Computer Society Annual Symposium on VLSI, 347-348, 2011
32011
New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
T Zhang, V Pudi, W Liu
IEEE Transactions on Circuits and Systems II: Express Briefs 66 (7), 1232-1236, 2018
22018
Lightweight and high performance SHA-256 using architectural folding and 4-2 adder compressor
MM Wong, V Pudi, A Chattopadhyay
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
22018
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