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Mark Helm
Mark Helm
Adresse e-mail validée de micron.com
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Memory kink checking
U Chandrasekhar, M Helm
US Patent 8,482,975, 2013
3932013
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory
T Tanaka, M Helm, T Vali, R Ghodsi, K Kawai, JK Park, S Yamada, F Pan, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 142-144, 2016
1412016
Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate
M Helm, C Dennison
US Patent 5,624,863, 1997
1351997
Formation of standard voltage threshold and low voltage threshold MOSFET devices
M Helm, X Zhou
US Patent 7,755,146, 2010
1212010
Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
CH Dennison, M Helm
US Patent 5,534,449, 1996
761996
19.1 A 128Gb MLC NAND-Flash device using 16nm planar cell
M Helm, JK Park, A Ghalam, J Guo, C wan Ha, C Hu, H Kim, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
722014
A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology
G Naso, L Botticchio, M Castelli, C Cerafogli, M Cichocki, P Conenna, ...
2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013
342013
Source lines for NAND memory devices
MA Helm, RW Lindsay
US Patent 7,112,488, 2006
322006
Energy-efficient deep in-memory architecture for NAND flash memories
SK Gonugondla, M Kang, Y Kim, M Helm, S Eilert, N Shanbhag
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
312018
CMOS integrated circuitry with Halo and LDD regions
CH Dennison, M Helm
US Patent 5,747,855, 1998
311998
Three dimensional memory control circuitry
M Helm, JS Hoei, A Yip, D Nguyen
US Patent 9,202,536, 2015
262015
Methods, devices, and systems for data sensing in a memory system
MA Helm, U Chandrasekhar
US Patent 8,631,288, 2014
252014
Method for avoiding lithographic rounding effects for semiconductor fabrication
CJ Petti, AN Stolmeijer, MA Helm
US Patent 5,523,258, 1996
251996
Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods
AS Yip, MA Helm, R Ghodsi
US Patent 9,070,442, 2015
242015
Method of forming CMOS integrated circuitry having halo regions
CH Dennison, M Helm
US Patent 5,776,806, 1998
231998
Method of forming CMOS integrated circuitry
CH Dennison, M Helm
US Patent 5,683,927, 1997
211997
Three dimensional storage cell array with highly dense and scalable word line design approach
D Thimmegowda, A Yip, M Helm, LI Yongna
US Patent 10,043,751, 2018
202018
Apparatus, systems, and methods to operate a memory
K Sakui, T Hasegawa, M Helm
US Patent 9,972,391, 2018
192018
Method and system to obtain state confidence data using multistrobe read of a non-volatile memory
M Goldman, KK Parat, P Kalavade, NR Franklin, M Helm
US Patent 9,754,683, 2017
192017
Efficient fabrication process for dual well type structures
MA Helm
US Patent 6,268,250, 2001
192001
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