| A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed … X Zhao, Y Chen, PI Mak, RP Martins 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020 | 23 | 2020 |
| A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS X Zhao, Y Chen, PI Mak, RP Martins 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 229-232, 2019 | 23* | 2019 |
| Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter X Ge, Y Chen, X Zhao, PI Mak, RP Martins IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (10 …, 2019 | 22 | 2019 |
| A m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4–44 GHz) Y Chen, Z Yang, X Zhao, Y Huang, PI Mak, RP Martins IEEE Solid-State Circuits Letters 2 (5), 37-40, 2019 | 22 | 2019 |
| A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative- Cell X Zhao, Y Chen, PI Mak, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers 66 (9), 3330-3339, 2019 | 18 | 2019 |
| A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS X Zhao, Y Chen, L Wang, PI Mak, F Maloberti, RP Martins IEEE Journal of Solid-State Circuits, 2022 | 11 | 2022 |
| A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 … X Zhao, Y Chen, PI Mak, RP Martins IEEE Journal of Solid-State Circuits 57 (2), 546-561, 2021 | 10 | 2021 |
| A sub-0.25 pJ/bit 47.6-to-58.8 Gb/s reference-less FD-less single-loop PAM-4 bang-bang CDR with a deliberately-current-mismatch frequency acquisition technique in 28nm CMOS X Zhao, Y Chen, L Wang, PI Mak, F Maloberti, RP Martins 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 131-134, 2021 | 9 | 2021 |
| A 0.01-mm2 1.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase X Zhao, Y Chen, X Zheng, PI Mak, RP Martins 2021 IEEE MTT-S International Microwave Symposium (IMS), 386-389, 2021 | 5 | 2021 |
| A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current-Mismatch Wide-Frequency-Acquisition Technique L Wang, Y Chen, C Yang, X Zhao, PI Mak, F Maloberti, RP Martins IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 2 | 2023 |
| A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply Z Dong, S Liu, X Zhao, B Hao, H Liang, H Han, M Wang, W Han, Z Zhu 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 1 | 2023 |
| A 10.8-to-37.4 Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme L Wang, Y Chen, C Yang, X Zhao, PI Mak, F Maloberti, RP Martins 2022 29th IEEE International Conference on Electronics, Circuits and Systems …, 2022 | 1 | 2022 |
| A 0.14-to-0.29-pJ/bit 14-GBaud/s trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS RPM Xiaoteng Zhao, Yong Chen, Pui-In Mak IEEE Transactions on Circuits and Systems I: Regular Papers 68 (1), 89-102, 2021 | | 2021 |
Rui MartinsLife Fellow IEEE, Chair Professor (ECE), Director of IME, University of MacauVerified email at um.edu.mo
