Hongyan Xia
Title
Cited by
Cited by
Year
Capability hardware enhanced risc instructions: Cheri instruction-set architecture (version 5)
RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ...
University of Cambridge, Computer Laboratory, 2016
562016
Efficient tagged memory
A Joannou, J Woodruff, R Kovacsics, SW Moore, A Bradbury, H Xia, ...
2017 IEEE International Conference on Computer Design (ICCD), 641-648, 2017
452017
CHERI Concentrate: Practical Compressed Capabilities
J Woodruff, A Joannou, H Xia, B Davis, PG Neumann, RNM Watson, ...
IEEE Transactions on Computers, 2019
292019
CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety
H Xia, J Woodruff, S Ainsworth, NW Filardo, M Roe, A Richardson, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
232019
Cornucopia: Temporal Safety for CHERI Heaps
NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ...
2020 IEEE Symposium on Security and Privacy (SP). Los Alamitos, CA, USA …, 2020
152020
CheriRTOS: A Capability Model for Embedded Devices
H Xia, J Woodruff, H Barral, L Esswood, A Joannou, R Kovacsics, ...
2018 IEEE 36th International Conference on Computer Design (ICCD), 92-99, 2018
92018
Capability memory protection for embedded systems
H Xia
University of Cambridge, Computer Laboratory, 2021
2021
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