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Binod Kumar
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A methodology for trace signal selection to improve error detection in post-silicon validation
B Kumar, A Jindal, V Singh, M Fujita
2017 30th International Conference on VLSI Design and 2017 16th …, 2017
192017
Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications
V Kumar, A Singh, S Upadhyay, B Kumar
Journal of Circuits, Systems and Computers 28 (10), 1950171, 2019
152019
Analyzing hardware security properties of processors through model checking
B Kumar, AK Jaiswal, VS Vineesh, R Shinde
2020 33rd International Conference on VLSI Design and 2020 19th …, 2020
122020
Post-silicon observability enhancement with topology based trace signal selection
B Kumar, A Jindal, M Fujita, V Singh
2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017
122017
Deeppeep: Exploiting design ramifications to decipher the architecture of compact dnns
NK Jha, S Mittal, B Kumar, G Mattela
ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (1), 1-25, 2020
112020
Post-silicon gate-level error localization with effective and combined trace signal selection
B Kumar, K Basu, M Fujita, V Singh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
112018
RTL level trace signal selection and coverage estimation during post-silicon validation
B Kumar, K Basu, M Fujita, V Singh
2017 IEEE International High Level Design Validation and Test Workshop …, 2017
112017
Combining restorability and error detection ability for effective trace signal selection
B Kumar, A Jindal, M Fujita, V Singh
Proceedings of the on Great Lakes Symposium on VLSI 2017, 191-196, 2017
112017
Testing multiple stuck-at faults of robdd based combinational circuit design
T Shah, A Matrosova, B Kumar, M Fujita, V Singh
2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017
82017
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture
B Kumar, B Nehru, B Pandey, V Singh, J Tudu
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
62016
A methodology to capture fine-grained internal visibility during multisession silicon debug
B Kumar, J Adhaduk, K Basu, M Fujita, V Singh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4 …, 2020
52020
Silicon debug with maximally expanded internal observability using nearest neighbor algorithm
A Jindal, B Kumar, N Jindal, M Fujita, V Singh
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 46-51, 2018
52018
Improving post-silicon error detection with topological selection of trace signals
B Kumar, K Basu, A Jindal, M Fujita, V Singh
2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017
52017
Validating multi-processor cache coherence mechanisms under diminished observability
B Kumar, AK Bhosale, M Fujita, V Singh
2019 IEEE 28th Asian Test Symposium (ATS), 99-995, 2019
42019
Performance modelling of heterogeneous ISA multicore architectures
NK Boran, RP Meghwal, K Sharma, B Kumar, V Singh
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
42016
A trace signal selection algorithm for improved post-silicon debug
B Kumar, A Jindal, V Singh
2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016
42016
Enhanced design debugging with assistance from guidance-based model checking
VS Vineesh, B Kumar, R Shinde, N Sharma, M Fujita, V Singh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
32020
Identification of effective guidance hints for better design debugging by formal methods
VS Vineesh, B Kumar, J Adhaduk
VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019
32019
Elura: A methodology for post-silicon gate-level error localization using regression analysis
A Jindal, B Kumar, K Basu, M Fujita
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
32018
Blood pressure estimation from ECG data using XGBoost and ANN for wearable devices
S Banerjee, B Kumar, AP James, JN Tripathi
2022 29th IEEE International Conference on Electronics, Circuits and Systems …, 2022
22022
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