Oswaldo Cadenas
Oswaldo Cadenas
Senior Lecturer, London South Bank University, UK
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Fast median calculation method
J Cadenas, GM Megson, RS Sherratt, P Huerta
Electronics Letters 48 (10), 558, 2012
Functional verification: approaches and challenges
A Molina, O Cadenas
Latin American applied research 37 (1), 65-69, 2007
A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers
RS Sherratt, O Cadenas, N Goswami
IEEE Transactions on Consumer Electronics 51 (3), 798-802, 2005
Parallel pipelined array architectures for real-time histogram computation in consumer devices
JO Cadenas, RS Sherratt, P Huerta, WC Kao
Consumer Electronics, IEEE Transactions on 57 (4), 1460-1464, 2011
A clocking technique for FPGA pipelined designs
O Cadenas, G Megson
Journal of Systems Architecture 50 (11), 687-696, 2004
Power performance with gated clocks of a pipelined Cordic core
O Cadenas, G Megson
ASIC, 2003. Proceedings. 5th International Conference on 2, 1226-1230, 2003
Median filter architecture by accumulative parallel counters
JO Cadenas, GM Megson, RS Sherratt
IEEE Transactions on Circuits and Systems II: Express Briefs 62 (7), 661-665, 2015
Virtualization for cost-effective teaching of assembly language programming
JO Cadenas, RS Sherratt, D Howlett, CG Guy, KO Lundqvist
IEEE Transactions on Education 58 (4), 282-288, 2015
Rapid preconditioning of data for accelerating convex hull computations
J Cadenas, GM Megson
Electronics Letters 50 (4), 270-272, 2014
A new organization for a perceptron-based branch predictor and its FPGA implementation
O Cadenas, G Megson, D Jones
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design …, 2005
Major differences of cloud computing adoption in universities: Europe vs. Middle East
M Odeh, K Warwick, O Cadenas
Journal of Emerging Trends in Computing and Information Sciences 5 (12), 948-952, 2014
Experiences applying OVM 2.0 to an 8B/10B RTL design
O Cadenas, E Todorovich
2009 5th Southern Conference on Programmable Logic (SPL), 1-8, 2009
Fpga based dual carrier modulation soft mapper and demapper for the mb-ofdm uwb platform
R Yang, RS Sherratt, O Cadenas
Proc. of the Annual Postgraduate Symposium, 2007
Pipelined median architecture
J Cadenas
Electronics Letters 51 (24), 1999-2001, 2015
Parallel pipelined histogram architectures
J Cadenas, RS Sherratt, P Huerta
Electronics Letters 47 (20), 1118-1120, 2011
A practical low cost architecture for a MB-OFDM equalizer (ECMA-368)
RS Sherratt, O Cadenas, R Yang
2007 IEEE International Symposium on Consumer Electronics, 1-4, 2007
C-slow retimed parallel histogram architectures for consumer imaging devices
J Cadenas, RS Sherratt, P Huerta, WC Kao, GM Megson
IEEE Transactions on Consumer Electronics 59 (2), 291-295, 2013
A double data rate architecture for OFDM based wireless consumer devices
RS Sherratt, O Cadenas
IEEE Transactions on Consumer Electronics 56 (1), 23-26, 2010
Pipelining considerations for an FPGA case
O Cadenas, G Megson
Proceedings Euromicro Symposium on Digital Systems Design, 276-283, 2001
Preconditioning 2D integer data for fast convex hull computations
JO Cadenas, GM Megson, CL Luengo Hendriks
Plos one 11 (3), e0149860, 2016
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