Michele Franceschini
TitleCited byYear
Phase change memory technology
GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ...
Journal of Vacuum Science & Technology B, Nanotechnology andá…, 2010
7512010
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MK Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
Proceedings of the 42nd annual IEEE/ACM international symposium oná…, 2009
6792009
Improving read performance of phase change memories via write cancellation and write pausing
MK Qureshi, MM Franceschini, LA Lastras-Montano
HPCA-16 2010 The Sixteenth International Symposium on High-Performanceá…, 2010
2902010
Morphable memory system: A robust architecture for exploiting multi-level phase change memories
MK Qureshi, MM Franceschini, LA Lastras-Monta˝o, JP Karidis
ACM SIGARCH Computer Architecture News 38 (3), 153-162, 2010
1952010
PreSET: improving performance of phase change memories by exploiting asymmetry in write times
MK Qureshi, MM Franceschini, A Jagmohan, LA Lastras
ACM SIGARCH Computer Architecture News 40 (3), 380-391, 2012
1452012
Resistive memory devices having a not-and (NAND) structure
MJ Breitwisch, GS Ditlow, MM Franceschini, LA Lastras-Montano, ...
US Patent 8,107,276, 2012
1032012
Practical and secure pcm systems by online detection of malicious write streams
MK Qureshi, A Seznec, LA Lastras, MM Franceschini
2011 IEEE 17th International symposium on high performance computerá…, 2011
862011
Fundamental performance limits of communications systems impaired by impulse noise
R Pighi, M Franceschini, G Ferrari, R Raheli
IEEE Transactions on Communications 57 (1), 171-182, 2009
782009
Does the performance of LDPC codes depend on the channel?
M Franceschini, G Ferrari, R Raheli
IEEE Transactions on communications 54 (12), 2129-2132, 2006
722006
Adaptive endurance coding of non-volatile memories
MM Franceschini, A Jagmohan, JP Karidis, LA Lastras-Montano
US Patent 8,341,501, 2012
65*2012
Iterative write pausing techniques to improve read latency of memory systems
MM Franceschini, LA Lastras-Montano, MK Qureshi, V Srinivasan
US Patent 8,004,884, 2011
642011
Serial concatenation of LDPC codes and differential modulations
M Franceschini, G Ferrari, R Raheli, A Curtoni
IEEE Journal on Selected Areas in Communications 23 (9), 1758-1768, 2005
642005
Bad block management for flash memory
JA Bivens, MM Franceschini, A Jagmohan
US Patent 8,560,922, 2013
512013
Write amplification reduction in NAND flash through multi-write coding
A Jagmohan, M Franceschini, L Lastras
2010 IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST), 1-6, 2010
512010
Multi-Write endurance and error control coding of Non-Volatile memories
MM Franceschini, A Jagmohan
US Patent 8,769,374, 2014
452014
Non-volatile memories with enhanced write performance and endurance
MM Franceschini, A Jagmohan, LA Lastras-Montano, M Sharma
US Patent 8,176,235, 2012
432012
LDPC coded modulations
M Franceschini, G Ferrari, R Raheli
Springer, 2009
422009
Architectural design for next generation heterogeneous memory systems
A Bivens, P Dube, M Franceschini, J Karidis, L Lastras, M Tsao
2010 IEEE International Memory Workshop, 1-4, 2010
372010
Estimation of closeness of topics based on graph analytics
MM Franceschini, A Jagmohan, LA Lastras-Montano, L Soares
US Patent 9,542,503, 2017
362017
On the lifetime of multilevel memories
LA Lastras-Monta˝o, M Franceschini, T Mittelholzer, J Karidis, M Wegman
2009 IEEE International Symposium on Information Theory, 1224-1228, 2009
292009
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