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A low fragmentation heuristic for task placement in 2D RTR HW management
J Tabero, J Septién, H Mecha, D Mozos
International Conference on Field Programmable Logic and Applications, 241-250, 2004
Task placement heuristics based on 3D-adjacency and look-ahead in reconfigurable systems
J Tabero, J Septién, H Mecha, D Mozos
Asia and South Pacific Conference on Design Automation, 2006., 6 pp., 2006
A vertex-list approach to 2d hw multitasking management in rtr fpgas
J Tabero, J Septién, H Mecha, D Mozos, S Roman
Design of Circuits and Integrated Systems (DCIS), 545-550, 2003
A method for area estimation of data-path in high level synthesis
H Mecha, M Fernandez, F Tirado, J Septien, D Mozos, K Olcoz
IEEE transactions on computer-aided design of integrated circuits and …, 1996
A methodology to emulate single event upsets in flip-flops using FPGAs through partial reconfiguration and instrumentation
F Serrano, JA Clemente, H Mecha
IEEE Transactions on Nuclear Science 62 (4), 1617-1624, 2015
Comparison of the susceptibility to soft errors of SRAM-based FPGA error correction codes implementations
S Liu, G Sorrenti, P Reviriego, F Casini, JA Maestro, M Alderighi, H Mecha
IEEE Transactions on Nuclear Science 59 (3), 619-624, 2012
Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays
S Roman, H Mecha, D Mozos, J Septién
IET Computers & Digital Techniques 2 (6), 401-412, 2008
Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs
JA Clemente, W Mansour, R Ayoubi, F Serrano, H Mecha, H Ziade, ...
Neurocomputing 171, 1606-1609, 2016
Allocation heuristics and defragmentation measures for reconfigurable systems management
J Tabero, J Septién, H Mecha, D Mozos
Integration 41 (2), 281-296, 2008
2d defragmentation heuristics for hardware multitasking on reconfigurable devices
J Septién, H Mecha, D Mozos, J Tabero
Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006
FIDIAS: an integral approach to high-level synthesis
J Septién, D Mozos, JF Tirado, R Hermida, H Mecha
IEE Proceedings-Circuits, Devices and Systems 142 (4), 227-235, 1995
Factores psicosociales asociados al estrés estudiantil de un colegio privado de ciudad de Panamá
J Forero, H López, N Pardo
Universidad de La Sabana, 2004
Statistical anomalies of bitflips in SRAMs to discriminate SBUs from MCUs
JA Clemente, FJ Franco, F Villa, M Baylac, S Rey, H Mecha, JA Agapito, ...
IEEE Transactions on Nuclear Science 63 (4), 2087-2094, 2016
Telenovelas en México: Nuestras íntimas extrañas
A Cueva, C Estrada, A Garnica, R Jara, H López, G Orozco, S Soto
México: Grupo Delphi, 2011
3d fpga resource management and fragmentation metric for hardware multitasking
JA Valero, J Septién, D Mozos, H Mecha
2009 IEEE International Symposium on Parallel & Distributed Processing, 1-7, 2009
A hardware/software partitioning and scheduling approach for embedded systems with low-power and high performance requirements
J Resano, D Mozos, E Pérez, H Mecha, J Septién
International Workshop on Power and Timing Modeling, Optimization and …, 2003
A macroscopic time and cost estimation model allowing task parallelism and hardware sharing for the codesign partitioning process
JA Maestro, D Mozos, H Mecha
Proceedings Design, Automation and Test in Europe, 218-225, 1998
Single events in a COTS soft-error free SRAM at low bias voltage induced by 15-MeV neutrons
JA Clemente, FJ Franco, F Villa, M Baylac, P Ramos, V Vargas, H Mecha, ...
IEEE Transactions on Nuclear Science 63 (4), 2072-2079, 2016
Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking
J Septién, D Mozos, H Mecha, J Tabero, MAG de Dios
2008 IEEE International Parallel & Distributed Processing Symposium, 1-8, 2008
Constant complexity management of 2D HW multitasking in run-time reconfigurable FPGAs
S Román, J Septién, H Mecha, D Mozos
International Workshop on Applied Reconfigurable Computing, 187-192, 2006
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